Suchergebnisse - acm: b.: hardware/b.6: logic design/b.6.3: design ad/b.6.3.2: optimization

Contributions to Program Optimization and High-Level Synthesis ; Contributions à l'optimisation de programmes et à la synthèse de circuits haut-niveau

Autoren: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Centre Inria de l'Université Grenoble Alpes et al.

Weitere Verfasser: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Centre Inria de l'Université Grenoble Alpes et al.

Quelle: https://inria.hal.science/tel-02151877 ; Hardware Architecture [cs.AR]. ENS de Lyon, 2019.

Schlagwörter: High-Level Synthesis, Compilation Techniques, Automatic Parallelization, Compilation, Parallélisation automatique, Synthèse haut-niveau, FPGA, ACM: B.: Hardware, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL]

Verfügbarkeit: https://inria.hal.science/tel-02151877
https://inria.hal.science/tel-02151877v2/document
https://inria.hal.science/tel-02151877v2/file/hdr-alias.pdf

A semiempirical model for wakeup time estimation in power-gated logic clusters

Autoren: Tovinakere Dwarakanath, Vivek Sentieys, Olivier Derrien, Steven et al.

Weitere Verfasser: Tovinakere Dwarakanath, Vivek Sentieys, Olivier Derrien, Steven et al.

Quelle: The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012 ; https://inria.hal.science/hal-00752606 ; The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012, Jun 2012, San Fransisco, United States. pp.48-55

Schlagwörter: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.7: VLSI (very large scale integration), ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Geographisches Schlagwort: San Fransisco, United States

Verfügbarkeit: https://inria.hal.science/hal-00752606

Dynamic Profiling and Fuzzy-Logic-Based Optimization of Sensor Network Platforms.

Autoren: LIZARRAGA, ADRIAN LYSECKY, ROMAN LYSECKY, SUSAN et al.

Quelle: ACM Transactions on Embedded Computing Systems; Dec2013, Vol. 13 Issue 3, p51:1-51:29, 29p

Schlagwörter: DYNAMICAL systems, FUZZY logic, MATHEMATICAL optimization, SENSOR networks, APPLICATION software, COMPUTER engineering

SHIFT: Selective Hardware Information Flow Tracking Driven by Deterministic Constraints.

Autoren: Sun, Haodong Yang, Zhi Jin, Shuyuan et al.

Quelle: ACM Journal on Emerging Technologies in Computing Systems; Oct2025, Vol. 21 Issue 4, p1-16, 16p

Schlagwörter: HARDWARE design & construction, CONSTRAINED optimization, MATHEMATICAL optimization, SCIENTIFIC apparatus & instruments, RISK assessment

Structured Design of Complex Hardware Microarchitectures Based on Explicit Generic Implementations of Custom Microarchitectural Mechanisms.

Autoren: Antonov, Alexander

Quelle: Electronics (2079-9292); Apr2022, Vol. 11 Issue 7, p1055-N.PAG, 13p

Schlagwörter: COMPUTER engineering, COMPUTER systems, SOURCE code, SYSTEMS design, HARDWARE, PROGRAMMABLE logic devices

Throughput and FIFO Sizing: an Application to Latency-Insensitive Design

Autoren: Boucaron, Julien Coadou, Anthony de Simone, Robert et al.

Weitere Verfasser: Boucaron, Julien Coadou, Anthony de Simone, Robert et al.

Quelle: https://inria.hal.science/inria-00381644 ; [Research Report] RR-6919, INRIA. 2009, pp.19.

Schlagwörter: FIFO sizing, Buffer sizing, Throughput, Latency-Insensitive Design, Marked Graphs, ACM: F.: Theory of Computation/F.1: COMPUTATION BY ABSTRACT DEVICES/F.1.1: Models of Computation, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS, [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Verfügbarkeit: https://inria.hal.science/inria-00381644
https://inria.hal.science/inria-00381644v1/document
https://inria.hal.science/inria-00381644v1/file/RR-6919.pdf

A Hybrid Nano/CMOS Dynamically Reconfigurable System-Part II: Design Optimization Flow.

Autoren: Wei Zhang Jha, Niraj K. Li Shang

Quelle: ACM Journal on Emerging Technologies in Computing Systems; 2009, Vol. 5 Issue 3, p13.1-13:31, 31p, 11 Diagrams, 7 Charts, 1 Graph

Schlagwörter: COMPLEMENTARY metal oxide semiconductors, COMPUTER storage devices, ADAPTIVE computing systems, DIGITAL electronics, MICROPROCESSORS, PROGRAMMABLE logic devices, ENGINEERING design

Automatic Differentiation Accelerated Shape Optimization Approaches to Photonic Inverse Design in FDFD/FDTD.

Autoren: Hooten, Sean Sun, Peng Gantz, Liron et al.

Quelle: Laser & Photonics Reviews; 1/22/2025, Vol. 19 Issue 2, p1-22, 22p

Schlagwörter: AUTOMATIC differentiation, PHOTONICS, STRUCTURAL optimization, SENSITIVITY analysis, FINITE difference time domain method, JACOBIAN matrices

Novel Design of Resource‐Constrained Quantum Reversible Logic Gates at Optimal Cost and Depth.

Autoren: Prajapati, Mamtha Killana, Kalyan Babu Curreli, Nicola

Quelle: Journal of Nanotechnology; 8/6/2025, Vol. 2025, p1-17, 17p

Schlagwörter: QUANTUM computing, REVERSIBLE computing, MATHEMATICAL optimization, QUANTUM gates, CIRCUIT complexity, NANOTECHNOLOGY

Finding near-perfect parameters for hardware and code optimizations with automatic multi-objective design space explorations.

Autoren: Jahr, Ralf Calborean, Horia Vintan, Lucian et al.

Quelle: Concurrency & Computation: Practice & Experience; Jun2015, Vol. 27 Issue 9, p2196-2214, 19p

Schlagwörter: PARAMETER estimation, COMPUTER software, CODING theory, MATHEMATICAL optimization, AUTOMATION, COMPUTER architecture

Dynamic Variable Stage Pipeline: an Implementation of its Control

Autoren: Boucaron, Julien Coadou, Anthony Models and methods of analysis and optimization for systems with real-time and embedding constraints (AOSTE) et al.

Weitere Verfasser: Boucaron, Julien Coadou, Anthony Models and methods of analysis and optimization for systems with real-time and embedding constraints (AOSTE) et al.

Quelle: https://inria.hal.science/inria-00381563 ; [Research Report] RR-6918, INRIA. 2009, pp.15.

Schlagwörter: Variable length pipeline, Variable stage pipeline, Pipeline stage unification, Low Power, Leakage, Energy, Throughput, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Verfügbarkeit: https://inria.hal.science/inria-00381563
https://inria.hal.science/inria-00381563v1/document
https://inria.hal.science/inria-00381563v1/file/RR-6918.pdf

Active Leakage Power Optimization for FPGAs.

Autoren: Anderson, Jason H. Najm, Farid N.

Quelle: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Mar2006, Vol. 25 Issue 3, p423-437, 15p, 2 Black and White Photographs, 5 Charts, 17 Graphs

Schlagwörter: FIELD programmable gate arrays, COMPLEMENTARY metal oxide semiconductors, COMPUTER-aided design, GATE array circuits, LOGIC circuits, ELECTRONIC circuit design, COMPUTER engineering

Dressi: A Hardware‐Agnostic Differentiable Renderer with Reactive Shader Packing and Soft Rasterization.

Autoren: Takimoto, Yusuke Sato, Hiroyuki Takehara, Hikari et al.

Quelle: Computer Graphics Forum; May2022, Vol. 41 Issue 2, p13-27, 15p, 7 Color Photographs, 1 Black and White Photograph, 6 Diagrams, 5 Charts, 3 Graphs

Schlagwörter: AUTOMATIC differentiation, COMPUTER vision, COMPUTER graphics, ROBUST optimization, SYSTEMS design, MATHEMATICAL optimization, RENDERING (Computer graphics)

Hardware–Software Co-Optimization of Long-Latency Stochastic Computing.

Autoren: Aygun, Sercan Kouhalvandi, Lida Najafi, M. Hassan et al.

Quelle: IEEE Embedded Systems Letters; Dec2023, Vol. 15 Issue 4, p190-193, 4p

Mining parametric temporal logic properties in model-based design for cyber-physical systems.

Autoren: Hoxha, Bardh Dokhanchi, Adel Fainekos, Georgios

Quelle: International Journal on Software Tools for Technology Transfer; Feb2018, Vol. 20 Issue 1, p79-93, 15p

Schlagwörter: CYBER physical systems, MATHEMATICAL logic, COMPUTER software development, PARETO analysis, MATHEMATICAL optimization

ARMHEx: A hardware extension for DIFT on ARM-based SoCs

Autoren: Wahab, Muhammad Abdul Cotret, Pascal Nasr Allah, Mounir et al.

Weitere Verfasser: Wahab, Muhammad Abdul Cotret, Pascal Nasr Allah, Mounir et al.

Quelle: 2017 27th International Conference on Field Programmable Logic and Applications (FPL)
https://hal.science/hal-01558473
2017 27th International Conference on Field Programmable Logic and Applications (FPL), Sep 2017, Ghent, Belgium. ⟨10.23919/fpl.2017.8056767⟩
https://www.fpl2017.org/

Schlagwörter: Information Flow Tracking, SoC, Zynq, Zynq SoC, CoreSight, ARM Debug components, IFT, Dynamic information flow tracking, DIFT, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.6: Security and Protection, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Geographisches Schlagwort: Ghent, Belgium

Verfügbarkeit: https://hal.science/hal-01558473
https://hal.science/hal-01558473v1/document
https://hal.science/hal-01558473v1/file/bare_conf.pdf
https://doi.org/10.23919/fpl.2017.8056767

Technology/System Co-Optimization for FPGA Using Emerging Reconfigurable Logic Device.

Autoren: Lu, Sheng Shang, Liuting Jung, Sungyong et al.

Quelle: ACM Journal on Emerging Technologies in Computing Systems; Jul2025, Vol. 21 Issue 3, p1-21, 21p

Schlagwörter: FIELD programmable gate arrays, PROGRAMMABLE logic devices, DESIGN techniques, MATHEMATICAL optimization, INTEGRATED circuits, BENCHMARK testing (Engineering)

Polynomial inversion hardware accelerator for post quantum algorithm.

Autoren: Divya, B Raja Sekar, K David Selvakumar, A et al.

Quelle: Sādhanā: Academy Proceedings in Engineering Sciences; Dec2025, Vol. 50 Issue 4, p1-14, 14p

Schlagwörter: CRYPTOGRAPHY, POLYNOMIALS, ALGORITHMS, PROGRAMMABLE logic devices, COMPUTATIONAL complexity, OPTIMIZATION algorithms

SlackHammer: Logic Synthesis for Graceful Errors Under Frequency Scaling.

Autoren: Alan, Tanfer Henkel, Jorg

Quelle: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Nov2018, Vol. 37 Issue 11, p2802-2811, 10p

Schlagwörter: LOGIC circuit synthesis (Electronic design), CRITICAL path analysis, ERROR rates, APPROXIMATION theory, CROSS layer optimization, ELECTRONIC design automation, REAL-time computing

Design Time Optimization for Hardware Watermarking Protection of HDL Designs.

Autoren: Castillo, E. Morales, D. P. García, A. et al.

Quelle: Scientific World Journal; 3/15/2015, Vol. 2015, p1-14, 14p

Schlagwörter: HARDWARE, DIGITAL watermarking, COMPUTER hardware description languages, INTERNET protocols, DIGITAL signatures