Suchergebnisse - acm: b.: hardware/b.6: logic design/b.6.3: design ad/b.6.3.2: optimization
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Autoren: et al.
Weitere Verfasser: et al.
Quelle: https://inria.hal.science/tel-02151877 ; Hardware Architecture [cs.AR]. ENS de Lyon, 2019.
Schlagwörter: High-Level Synthesis, Compilation Techniques, Automatic Parallelization, Compilation, Parallélisation automatique, Synthèse haut-niveau, FPGA, ACM: B.: Hardware, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL]
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Autoren: et al.
Weitere Verfasser: et al.
Quelle: The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012 ; https://inria.hal.science/hal-00752606 ; The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012, Jun 2012, San Fransisco, United States. pp.48-55
Schlagwörter: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.7: VLSI (very large scale integration), ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]
Geographisches Schlagwort: San Fransisco, United States
Verfügbarkeit: https://inria.hal.science/hal-00752606
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Autoren: et al.
Quelle: ACM Transactions on Embedded Computing Systems; Dec2013, Vol. 13 Issue 3, p51:1-51:29, 29p
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Autoren: et al.
Quelle: ACM Journal on Emerging Technologies in Computing Systems; Oct2025, Vol. 21 Issue 4, p1-16, 16p
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Autoren: Antonov, Alexander
Quelle: Electronics (2079-9292); Apr2022, Vol. 11 Issue 7, p1055-N.PAG, 13p
Schlagwörter: COMPUTER engineering, COMPUTER systems, SOURCE code, SYSTEMS design, HARDWARE, PROGRAMMABLE logic devices
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Autoren: et al.
Weitere Verfasser: et al.
Quelle: https://inria.hal.science/inria-00381644 ; [Research Report] RR-6919, INRIA. 2009, pp.19.
Schlagwörter: FIFO sizing, Buffer sizing, Throughput, Latency-Insensitive Design, Marked Graphs, ACM: F.: Theory of Computation/F.1: COMPUTATION BY ABSTRACT DEVICES/F.1.1: Models of Computation, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS, [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]
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Autoren:
Quelle: ACM Journal on Emerging Technologies in Computing Systems; 2009, Vol. 5 Issue 3, p13.1-13:31, 31p, 11 Diagrams, 7 Charts, 1 Graph
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Autoren: et al.
Quelle: Laser & Photonics Reviews; 1/22/2025, Vol. 19 Issue 2, p1-22, 22p
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Autoren:
Quelle: Journal of Nanotechnology; 8/6/2025, Vol. 2025, p1-17, 17p
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Autoren: et al.
Quelle: Concurrency & Computation: Practice & Experience; Jun2015, Vol. 27 Issue 9, p2196-2214, 19p
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Autoren: et al.
Weitere Verfasser: et al.
Quelle: https://inria.hal.science/inria-00381563 ; [Research Report] RR-6918, INRIA. 2009, pp.15.
Schlagwörter: Variable length pipeline, Variable stage pipeline, Pipeline stage unification, Low Power, Leakage, Energy, Throughput, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems
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Autoren:
Quelle: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Mar2006, Vol. 25 Issue 3, p423-437, 15p, 2 Black and White Photographs, 5 Charts, 17 Graphs
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Autoren: et al.
Quelle: Computer Graphics Forum; May2022, Vol. 41 Issue 2, p13-27, 15p, 7 Color Photographs, 1 Black and White Photograph, 6 Diagrams, 5 Charts, 3 Graphs
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Autoren: et al.
Quelle: IEEE Embedded Systems Letters; Dec2023, Vol. 15 Issue 4, p190-193, 4p
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Autoren:
Quelle: International Journal on Software Tools for Technology Transfer; Feb2018, Vol. 20 Issue 1, p79-93, 15p
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Autoren: et al.
Weitere Verfasser: et al.
Quelle: 2017 27th International Conference on Field Programmable Logic and Applications (FPL)
https://hal.science/hal-01558473
2017 27th International Conference on Field Programmable Logic and Applications (FPL), Sep 2017, Ghent, Belgium. ⟨10.23919/fpl.2017.8056767⟩
https://www.fpl2017.org/Schlagwörter: Information Flow Tracking, SoC, Zynq, Zynq SoC, CoreSight, ARM Debug components, IFT, Dynamic information flow tracking, DIFT, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.6: Security and Protection, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems
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Autoren: et al.
Quelle: ACM Journal on Emerging Technologies in Computing Systems; Jul2025, Vol. 21 Issue 3, p1-21, 21p
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Autoren: et al.
Quelle: Sādhanā: Academy Proceedings in Engineering Sciences; Dec2025, Vol. 50 Issue 4, p1-14, 14p
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Autoren:
Quelle: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Nov2018, Vol. 37 Issue 11, p2802-2811, 10p
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Autoren: et al.
Quelle: Scientific World Journal; 3/15/2015, Vol. 2015, p1-14, 14p
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