Search Results - acm: b.: hardware/b.6: logic design/b.6.3: design ad/b.6.3.0: automatizacia synthesis

Design of hardware RGB to HMMD converter based on reversible logic.

Authors: Touil, Lamjed Ouni, Bouraoui

Source: IET Image Processing (Wiley-Blackwell); Aug2017, Vol. 11 Issue 8, p646-655, 10p

Subject Terms: REVERSIBLE computing, OPTICAL information processing, LOGIC design, QUANTUM information science, CELLULAR automata, DIGITAL electronics

Magma's Rajeev Madhavan to Provide Keynote Address at ISPD; ''The Death of Logic Synthesis''

Source: Business Wire, March 30, 2005

Bio-mimicking DNA fingerprint profiling for HLS watermarking to counter hardware IP piracy.

Authors: Sengupta A Bhui N Anshul A et al.

Source: Scientific reports [Sci Rep] 2024 Sep 28; Vol. 14 (1), pp. 22413. Date of Electronic Publication: 2024 Sep 28.

Publication Type: Journal Article

Journal Info: Publisher: Nature Publishing Group Country of Publication: England NLM ID: 101563288 Publication Model: Electronic Cited Medium: Internet ISSN: 2045-2322 (Electronic) Linking ISSN: 20452322 NLM ISO Abbreviation: Sci Rep Subsets: MEDLINE

MeSH Terms: Computer Security* , DNA Fingerprinting*/methods , Algorithms*, Humans ; Computers ; DNA

Area-efficient parallel adder with faithful approximation for image and signal processing applications.

Authors: Palanisamy, Gnanambikai Natarajan, Vijeyakumar Krishnasamy Sundaram, Kalaiselvi

Source: IET Image Processing (Wiley-Blackwell); 2019, Vol. 13 Issue 13, p2587-2594, 8p

Subject Terms: SIGNAL processing, IMAGE processing, LOGIC design, METAL oxide semiconductor field-effect transistors, BLOCK designs, TRANSISTORS, DELAY-tolerant networks

Field Programmable Gate Array Applications—A Scientometric Review.

Authors: Ruiz-Rosero, Juan Ramirez-Gonzalez, Gustavo Khanna, Rahul

Source: Computation; Dec2019, Vol. 7 Issue 4, p63-63, 1p

Subject Terms: FIELD programmable gate arrays, DIGITAL video, PROGRAMMABLE logic devices, DIGITAL signal processing, MAGNETIC suspension, SYSTEMS on a chip

Ultra-Low-Power and Robust Digital-Signal-Processing Hardware for Implantable Neural Interface Microsystems.

Authors: Narasimhan, Seetharam Chiel, Hillel J. Bhunia, Swarup

Source: IEEE Transactions on Biomedical Circuits & Systems; 04/01/2011, Vol. 5 Issue 2, p169-178, 10p

Logic Design for Custom LSIs / カスタムLSIの論理設計

Authors: Takashi NANYA 南谷 崇

Source: 計測と制御 / Journal of The Society of Instrument and Control Engineers. 1989, 28(10):861

Design of a pseudo-log image transform hardware accelerator in a high-level synthesis-based memory management framework.

Authors: Butt, Shahzad Ahmad Mancini, Stéphane Rousseau, Frédéric et al.

Source: Journal of Electronic Imaging; Sep/Oct2014, Vol. 23 Issue 5, p1-13, 13p

Subject Terms: TRANSFORM coding, IMAGE processing, KERNEL functions, COMPUTER memory management, LOOP tiling (Computer science)

Hardware architecture for projective model calculation and false match refining using random sample consensus algorithm.

Authors: Azimi, Ehsan Behrad, Alireza Ghaznavi-Ghoushchi, Mohammad Bagher et al.

Source: Journal of Electronic Imaging; Nov/Dec2016, Vol. 25 Issue 6, p1-15, 15p

Subject Terms: ALGORITHMS, IMAGING systems, IMAGE reconstruction, IMAGE registration, THREE-dimensional imaging

First-Order Logic Based Situational and Dynamic Interpretation of Natural Language Descriptions in Hardware Design Specifications / ハードウェア設計仕様における自然言語記述の一階論理に基づく状況的・動的解釈

Authors: Koichi KISE Kunio FUKUNAGA Noriaki IZUMI et al.

Source: 人工知能 / Journal of the Japanese Society for Artificial Intelligence. 1995, 10(5):720

Relaxed Fault-Tolerant Hardware Implementation of Neural Networks in the Presence of Multiple Transient Errors.

Authors: Mahdiani, Hamid Reza Fakhraie, Sied Mehdi Lucas, Caro

Source: IEEE Transactions on Neural Networks & Learning Systems; Aug2012, Vol. 23 Issue 8, p1215-1228, 14p

Subject Terms: ARTIFICIAL neural networks, COMPUTER input-output equipment, INTEGRATED circuit fault tolerance, HUMAN facial recognition software, LOGIC circuits

Synchoricity and NOCs could make Billion Gate custom hardware centric SOCs affordable

Authors: Hemani, Ahmed Jafri, Syed Masoumian, S.

Source: 2017 11th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2017.

Subject Terms: ASICs, Coarse Grain Reconfiguration, ESL, High-level Synthesis, NOCs, SOCs, Synchoricity, VLSI Design

File Description: print

Access URL: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-219649

A 0.13mJ/Prediction CIFAR-100 Fully Synthesizable Raster-Scan-Based Wired-Logic Processor in 16-nm FPGA

Authors: Atsutake Kosuge Dongzhu Li Mototsugu Hamada et al.

Source: IEICE Transactions on Electronics. :2023

Quantum computing hardware in the cloud: Should a computational chemist care?

Authors: Rossi, Alessandro Baity, Paul G. Schäfer, Vera M. et al.

Source: International Journal of Quantum Chemistry; 7/15/2021, Vol. 121 Issue 14, p1-15, 15p

Subject Terms: QUANTUM computing, QUANTUM computers, CLOUD computing, ION traps, CHEMISTS

ECG Authentication Hardware Design With Low-Power Signal Processing and Neural Network Optimization With Low Precision and Structured Compression.

Authors: Cherupally, Sai Kiran Yin, Shihui Kadetotad, Deepak et al.

Source: IEEE Transactions on Biomedical Circuits & Systems; Apr2020, Vol. 14 Issue 2, p198-208, 11p

Case study of an HEVC decoder application using high-level synthesis: intraprediction, dequantization, and inverse transform blocks.

Authors: Kammoun, Manel Atitallah, Ahmed Ben Ali, Karim M. A. et al.

Source: Journal of Electronic Imaging; May/Jun2019, Vol. 28 Issue 3, p33010-33010, 1p

Subject Terms: VIDEO coding, CASE studies, ALGORITHMS

Hardware acceleration of YOLOv7-tiny using high-level synthesis tools.

Authors: Hosseiny, Adib Jahanirad, Hadi

Source: Journal of Real-Time Image Processing; Aug2023, Vol. 20 Issue 4, p1-10, 10p

Compiler-assisted code generation for quantum computing: leveraging the unique properties of quantum architectures.

Authors: James, G. G. Ekong, A. P. Unyime, A. U. et al.

Source: Journal of Nigerian Society of Physical Sciences; May2025, Vol. 7 Issue 2, p1-12, 12p

Subject Terms: QUANTUM computing, QUBITS, COMPUTER software development, MATHEMATICAL optimization, COMPARATIVE studies

Digital Microfluidic Logic Gates and Their Application to Built-in Self-Test of Lab-on-Chip.

Authors: Yang Zhao Chakrabarty, Krishnendu

Source: IEEE Transactions on Biomedical Circuits & Systems; Aug2010, Vol. 4 Issue 4, p250-262, 13p

ON THE SYNTHESIS OF DECISION TABLES.

Authors: Srinivasan, B.

Source: Communications of the ACM. Feb1983, Vol. 26 Issue 2, p135-136. 2p.

Subject Terms: *DECISION logic tables, *SYSTEMS design, *DECISION making