Suchergebnisse - acm: b.: hardware/b.6: logic design/b.6.3: design ad/b.6.3.0: automation synthesis*

SlackHammer: Logic Synthesis for Graceful Errors Under Frequency Scaling.

Autoren: Alan, Tanfer Henkel, Jorg

Quelle: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Nov2018, Vol. 37 Issue 11, p2802-2811, 10p

Schlagwörter: LOGIC circuit synthesis (Electronic design), CRITICAL path analysis, ERROR rates, APPROXIMATION theory, CROSS layer optimization, ELECTRONIC design automation, REAL-time computing

FPGA Design Automation: A Survey.

Autoren: Chen, Deming Cong, Jason Pan, Peichen

Quelle: Foundations & Trends in Electronic Design Automation; 2006, Vol. 1 Issue 3, p195-330, 137p

Schlagwörter: COMPUTER-aided design, COMPUTER-aided engineering, ARCHITECTURE & technology, FIELD programmable gate arrays, PROGRAMMABLE logic devices, AUTOMATION, AUTOMATIC identification, CONTROL theory (Engineering)

Hardware Trojan Detection Using Machine Learning: A Tutorial.

Autoren: GUBBI, KEVIN IMMANUEL LATIBARI, BANAFSHEH SABER SRIKANTH, ANIRUDH et al.

Quelle: ACM Transactions on Embedded Computing Systems; May2023, Vol. 22 Issue 3, p1-26, 26p

Schlagwörter: MACHINE learning, ELECTRONIC design automation, WIRELESS power transmission, INTEGRATED circuit design, TRANSIENT analysis

Las Vegas to Host 23rd ACM/IEEE Design Automation Conference.

Quelle: IEEE Design & Test of Computers; 1986, Vol. 3 Issue 3, p6-13, 8p

HLS-based fast design space exploration of ad hoc hardware accelerators: A key tool for MPSoC synthesis on FPGA.

Autoren: Corre, Youenn Hoang, Van-Trinh Diguet, Jean-Philippe et al.

Quelle: Proceedings of the 2012 Conference on Design & Architectures for Signal & Image Processing; 1/ 1/2012, p1-8, 8p

Automated Synthesis of Digital Hardware.

Autoren: Hafer Parker

Quelle: IEEE Transactions on Computers; 1982, Vol. C-31 Issue 2, p93-109, 17p

SMatch: Structural Matching for Fast Resynthesis in FPGAs.

Autoren: Trapani Possignolo, Rafael Renau, Jose

Quelle: DAC: Annual ACM/IEEE Design Automation Conference; 2019, Issue 56, p1027-1032, 6p

Schlagwörter: FIELD programmable gate arrays, ELECTRONIC design automation, LOGIC circuit synthesis (Electronic design), AGILE software development, SOFTWARE engineering

A survey on partitioning models, solution algorithms and algorithm parallelization for hardware/software co-design.

Autoren: Hou, Neng Yan, Xiaohu He, Fazhi

Quelle: Design Automation for Embedded Systems; Jun2019, Vol. 23 Issue 1/2, p57-77, 21p

Schlagwörter: ELECTRONIC design automation, EMBEDDED computer systems, COMPUTER-aided design, NANOELECTRONICS, COMPUTER software

Hardware Design and Verification with Large Language Models: A Scoping Review, Challenges, and Open Issues.

Autoren: Abdollahi, Meisam Yeganli, Seyedeh Faegheh Baharloo, Mohammad et al.

Quelle: Electronics (2079-9292); Jan2025, Vol. 14 Issue 1, p120, 74p

Schlagwörter: LANGUAGE models, INTEGRATED circuit verification, ELECTRONIC design automation, DATA structures, RESEARCH questions

SALSA: Systematic Logic Synthesis of Approximate Circuits.

Autoren: Venkataramani, Swagath Sabne, Amit Kozhikkottu, Vivek et al.

Quelle: DAC: Annual ACM/IEEE Design Automation Conference; Jun2012, p796-801, 6p

Schlagwörter: ELECTRONIC design automation, ALGORITHMS, ALGEBRAIC logic, EUCLIDEAN algorithm, SCALABILITY

An Industrial View of Electronic Design Automation.

Autoren: MacMillen, Don Butts, Michael

Quelle: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Dec2000, Vol. 19 Issue 12, p1428, 21p, 5 Black and White Photographs

Schlagwörter: ELECTRONICS, ELECTRONIC systems, VERY large scale circuit integration, AUTOMATION, DESIGN

A semiempirical model for wakeup time estimation in power-gated logic clusters

Autoren: Tovinakere Dwarakanath, Vivek Sentieys, Olivier Derrien, Steven et al.

Weitere Verfasser: Tovinakere Dwarakanath, Vivek Sentieys, Olivier Derrien, Steven et al.

Quelle: The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012 ; https://inria.hal.science/hal-00752606 ; The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012, Jun 2012, San Fransisco, United States. pp.48-55

Schlagwörter: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.7: VLSI (very large scale integration), ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Geographisches Schlagwort: San Fransisco, United States

Verfügbarkeit: https://inria.hal.science/hal-00752606

Specification and Synthesis of Hardware Checkpointing and Rollback Mechanisms.

Autoren: Carven Chan Schwartz-Narbonne, Daniel Sethi, Divjyot et al.

Quelle: DAC: Annual ACM/IEEE Design Automation Conference; Jun2012, p1226-1232, 7p

Schlagwörter: ROLLBACK recovery (Computer science), RTL (Computer program language), COMPUTER hardware description languages, NETWORK routers, INTEGRATED circuit interconnections, NETWORK performance, SYSTEMS design

Structured Design of Complex Hardware Microarchitectures Based on Explicit Generic Implementations of Custom Microarchitectural Mechanisms.

Autoren: Antonov, Alexander

Quelle: Electronics (2079-9292); Apr2022, Vol. 11 Issue 7, p1055-N.PAG, 13p

Schlagwörter: COMPUTER engineering, COMPUTER systems, SOURCE code, SYSTEMS design, HARDWARE, PROGRAMMABLE logic devices

Methods for the Design and Analysis of Power Optimized Finite-State Machines Using Clock Gating.

Autoren: Chodorowski, Piotr

Quelle: AIP Conference Proceedings; 2017, Vol. 1906 Issue 1, p1-4, 4p, 2 Diagrams, 1 Chart

Schlagwörter: FINITE state machines, LOGIC circuit synthesis (Electronic design), VHDL (Computer hardware description language), LOGIC circuit design, OPTIMAL designs (Statistics), ENERGY consumption

Efficient Metrics and High-Level Synthesis for Dynamically Reconfigurable Logic.

Autoren: Meribout, Mahmoud Motomura, Masato

Quelle: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Jun2004, Vol. 12 Issue 6, p603-621, 19p, 2 Black and White Photographs, 19 Diagrams, 8 Charts, 1 Graph

Schlagwörter: ADAPTIVE computing systems, MULTIPLEXING, SCHEDULING, LOGIC design, ELECTRONIC circuit design, TELECOMMUNICATION

Lockit: A Logic Locking Automation Software.

Autoren: Kajtez, Nemanja Zhang, Yue Halak, Basel

Quelle: Electronics (2079-9292); Nov2021, Vol. 10 Issue 22, p2817, 1p

Schlagwörter: INTEGRATED circuits manufacturing, PYTHON programming language, DIGITAL technology, INTEGRATED circuit design, LOGIC, AUTOMATION software, ALGORITHMS

Bandwidth Optimization Through On-Chip Memory Restructuring for HLS.

Autoren: Jason Cong Peng Wei Cody Hao Yu et al.

Quelle: DAC: Annual ACM/IEEE Design Automation Conference; 2017, Issue 54, p493-498, 6p

Schlagwörter: COMPUTER hardware description languages, COMPUTER engineering -- Computer-aided design, HIGH level synthesis (Electronic design), ELECTRONIC design automation, DATA transmission systems

Microfluidics-Based Biochips: Technology Issues, Implementation Platforms, and Design-Automation Challenges.

Autoren: Su, Fei Chakrabarty, Krishnendu Fair, Richard B.

Quelle: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Feb2006, Vol. 25 Issue 2, p211-223, 13p

Schlagwörter: MICROFLUIDICS, DNA, BIOCHIPS, MOLECULAR biology, AUTOMATION, MEDICAL sciences

Evaluating Large Language Models for Automatic Register Transfer Logic Generation for Combinational Circuits via High-Level Synthesis.

Autoren: Swaroopa, Sneha Mukherjee, Rijoy Debnath, Anushka et al.

Quelle: Foundations & Trends in Electronic Design Automation; 2024, Vol. 14 Issue 4, p315-337, 23p

Schlagwörter: LANGUAGE models, COMBINATIONAL circuits, INTEGRATED circuit verification, C++, GRAPES