Search Results - acm: b.: hardware/b.6: logic design/b.6.3: design ad/b.6.3.0: automatic synthesis

Contributions to Program Optimization and High-Level Synthesis ; Contributions à l'optimisation de programmes et à la synthèse de circuits haut-niveau

Authors: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Centre Inria de l'Université Grenoble Alpes et al.

Contributors: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Centre Inria de l'Université Grenoble Alpes et al.

Source: https://inria.hal.science/tel-02151877 ; Hardware Architecture [cs.AR]. ENS de Lyon, 2019.

Subject Terms: High-Level Synthesis, Compilation Techniques, Automatic Parallelization, Compilation, Parallélisation automatique, Synthèse haut-niveau, FPGA, ACM: B.: Hardware, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL]

Availability: https://inria.hal.science/tel-02151877
https://inria.hal.science/tel-02151877v2/document
https://inria.hal.science/tel-02151877v2/file/hdr-alias.pdf

Model Driven Engineering Benefits for High Level Synthesis

Authors: Le Beux, Sébastien Marquet, Philippe Dekeyser, Jean-Luc et al.

Contributors: Le Beux, Sébastien Marquet, Philippe Dekeyser, Jean-Luc et al.

Source: https://inria.hal.science/inria-00311300 ; [Research Report] RR-6615, INRIA. 2008, pp.46.

Subject Terms: ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.1: Design Styles/B.6.1.5: Parallel circuits, ACM: B.: Hardware/B.8: PERFORMANCE AND RELIABILITY/B.8.2: Performance Analysis and Design Aids, ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.5: Model Development/I.6.5.0: Modeling methodologies, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS/C.3.2: Real-time and embedded systems, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Availability: https://inria.hal.science/inria-00311300
https://inria.hal.science/inria-00311300/document
https://inria.hal.science/inria-00311300/file/RR-6615.pdf

Time-redundancy transformations for adaptive fault-tolerant circuits

Authors: Burlyaev, Dmitry Fradet, Pascal Girault, Alain et al.

Contributors: Burlyaev, Dmitry Fradet, Pascal Girault, Alain et al.

Source: 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)
https://inria.hal.science/hal-01253111
2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Jun 2015, Montreal, Canada. ⟨10.1109/AHS.2015.7231164⟩

Subject Terms: digital circuits, fault tolerance, time redundancy, circuit transformation, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.3: Reliability and Testing/B.5.3.2: Redundant design, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.2: Design Aids/B.5.2.0: Automatic synthesis, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-PF]Computer Science [cs]/Performance [cs.PF]

Subject Geographic: Montreal

Time: Montreal, Canada

Availability: https://inria.hal.science/hal-01253111
https://doi.org/10.1109/AHS.2015.7231164

Evaluating Large Language Models for Automatic Register Transfer Logic Generation for Combinational Circuits via High-Level Synthesis.

Authors: Swaroopa, Sneha Mukherjee, Rijoy Debnath, Anushka et al.

Source: Foundations & Trends in Electronic Design Automation; 2024, Vol. 14 Issue 4, p315-337, 23p

Subject Terms: LANGUAGE models, COMBINATIONAL circuits, INTEGRATED circuit verification, C++, GRAPES

FPGA-Specific Synthesis of Loop-Nests with Pipelined Computational Cores

Authors: Alias, Christophe Pasca, Bogdan Plesco, Alexandru et al.

Contributors: Alias, Christophe Pasca, Bogdan Plesco, Alexandru et al.

Source: https://inria.hal.science/inria-00606977 ; [Research Report] RR-7674, INRIA. 2011, pp.33.

Subject Terms: High-Level Synthesis, Compiler, ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES/B.2.4: High-Speed Arithmetic, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS/C.3.3: Signal processing systems, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL], [INFO.INFO-IA]Computer Science [cs]/Computer Aided Engineering, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Availability: https://inria.hal.science/inria-00606977
https://inria.hal.science/inria-00606977v1/document
https://inria.hal.science/inria-00606977v1/file/RR-7674.pdf

Methods for the Design and Analysis of Power Optimized Finite-State Machines Using Clock Gating.

Authors: Chodorowski, Piotr

Source: AIP Conference Proceedings; 2017, Vol. 1906 Issue 1, p1-4, 4p, 2 Diagrams, 1 Chart

Subject Terms: FINITE state machines, LOGIC circuit synthesis (Electronic design), VHDL (Computer hardware description language), LOGIC circuit design, OPTIMAL designs (Statistics), ENERGY consumption

HLS-based fast design space exploration of ad hoc hardware accelerators: A key tool for MPSoC synthesis on FPGA.

Authors: Corre, Youenn Hoang, Van-Trinh Diguet, Jean-Philippe et al.

Source: Proceedings of the 2012 Conference on Design & Architectures for Signal & Image Processing; 1/ 1/2012, p1-8, 8p

Specification and Synthesis of Hardware Checkpointing and Rollback Mechanisms.

Authors: Carven Chan Schwartz-Narbonne, Daniel Sethi, Divjyot et al.

Source: DAC: Annual ACM/IEEE Design Automation Conference; Jun2012, p1226-1232, 7p

Subject Terms: ROLLBACK recovery (Computer science), RTL (Computer program language), COMPUTER hardware description languages, NETWORK routers, INTEGRATED circuit interconnections, NETWORK performance, SYSTEMS design

Structured Design of Complex Hardware Microarchitectures Based on Explicit Generic Implementations of Custom Microarchitectural Mechanisms.

Authors: Antonov, Alexander

Source: Electronics (2079-9292); Apr2022, Vol. 11 Issue 7, p1055-N.PAG, 13p

Subject Terms: COMPUTER engineering, COMPUTER systems, SOURCE code, SYSTEMS design, HARDWARE, PROGRAMMABLE logic devices

Operation- Centric Hardware Description and Synthesis.

Authors: Hoe, James C. Arvind

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Sep2004, Vol. 23 Issue 9, p1277-1288, 11p

Subject Terms: COMPUTER-aided design, INFORMATION theory, ALGORITHMS, INFORMATION science, SYSTEMS design, SEMANTICS

FPGA Design Automation: A Survey.

Authors: Chen, Deming Cong, Jason Pan, Peichen

Source: Foundations & Trends in Electronic Design Automation; 2006, Vol. 1 Issue 3, p195-330, 137p

Subject Terms: COMPUTER-aided design, COMPUTER-aided engineering, ARCHITECTURE & technology, FIELD programmable gate arrays, PROGRAMMABLE logic devices, AUTOMATION, AUTOMATIC identification, CONTROL theory (Engineering)

StitchUp: Automatic Control Flow Protection for High Level Synthesis Circuits.

Authors: Fleming, Shane T. Thomas, David B.

Source: DAC: Annual ACM/IEEE Design Automation Conference; Jun2016, p815-820, 6p

Subject Terms: ERROR detection (Information theory), LOGIC circuit synthesis (Electronic design), FIELD programmable gate arrays, DATA flow computing, DATA transmission systems, MATHEMATICAL models

Automatic Time-Redundancy Transformation for Fault-Tolerant Circuits

Authors: Burlyaev, Dmitry Fradet, Pascal Girault, Alain et al.

Contributors: Burlyaev, Dmitry Fradet, Pascal Girault, Alain et al.

Source: 23rd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA'15
https://inria.hal.science/hal-01095747
23rd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA'15, Feb 2015, Monterey, United States. ⟨10.1145/2684746.2689058⟩

Subject Terms: ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.3: Reliability and Testing, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.2: Design Aids/B.5.2.0: Automatic synthesis, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.2: Design Aids/B.5.2.4: Verification, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-PF]Computer Science [cs]/Performance [cs.PF]

Subject Geographic: Monterey, United States

Availability: https://inria.hal.science/hal-01095747
https://doi.org/10.1145/2684746.2689058

METHODS OF COMPUTATIONAL PROCESS SCHEDULING FOR SYNTHESIS OF HARDWARE MICROARCHITECTURE.

Authors: Antonov, Alexander Kustarev, Pavel Bykovskii, Sergey

Source: Proceedings of the International Multidisciplinary Scientific GeoConference SGEM; 2019, Vol. 19 Issue 1, p445-452, 8p

Subject Terms: SOFTWARE architecture, STRUCTURAL design, HARDWARE, DESIGN techniques, APPLICATION program interfaces, COMPUTER scheduling

Smart Vision Chip for colon exploration ; Smart Vision Chip pour l’exploration du colon

Authors: Chuquimia, Orlando Systèmes Electroniques (SYEL) LIP6 et al.

Contributors: Chuquimia, Orlando Systèmes Electroniques (SYEL) LIP6 et al.

Source: https://tel.archives-ouvertes.fr/tel-02494557 ; Imagerie médicale. Sorbonne Université, 2019. Français.

Subject Terms: Automatic polyp detection, intelligent endoscopic capsule, Hough transform, fuzzy trees, fuzzy forest, artificial vision and hardware accelerator, vision artificielle et accélérateur matériel, Détection automatique des polypes, capsule endoscopique intelligente, transformée d’Hough, arbres flous, forets floues, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: C.: Computer Systems Organization/C.5: COMPUTER SYSTEM IMPLEMENTATION, ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE/I.2.6: Learning, ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE/I.2.9: Robotics, ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE/I.2.10: Vision and Scene Understanding, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.7: Feature Measurement/I.4.7.5: Texture, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.0: General/I.4.0.1: Image processing software, [INFO.INFO-IM]Computer Science [cs]/Medical Imaging, [INFO.INFO-CV]Computer Science [cs]/Computer Vision and Pattern Recognition [cs.CV], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI], [INFO.INFO-RB]Computer Science [cs]/Robotics [cs.RO]

Relation: tel-02494557; https://tel.archives-ouvertes.fr/tel-02494557; https://tel.archives-ouvertes.fr/tel-02494557/document; https://tel.archives-ouvertes.fr/tel-02494557/file/thhese_archivage__N%C2%B0dossier.pdf

Availability: https://tel.archives-ouvertes.fr/tel-02494557
https://tel.archives-ouvertes.fr/tel-02494557/document
https://tel.archives-ouvertes.fr/tel-02494557/file/thhese_archivage__N%C2%B0dossier.pdf

CHAD: Combinatory Homomorphic Automatic Differentiation.

Authors: VÁKÁR, MATTHIJS SMEDING, TOM

Source: ACM Transactions on Programming Languages & Systems; Jul2022, Vol. 44 Issue 3, p1-49, 49p

Subject Terms: AUTOMATIC differentiation, PROGRAMMING languages, LOGIC, EXPRESSIVE language, LINEAR codes

Geographic Terms: CHAD

Automated Synthesis of Digital Hardware.

Authors: Hafer Parker

Source: IEEE Transactions on Computers; 1982, Vol. C-31 Issue 2, p93-109, 17p

Specification and synthesis of hardware checkpointing and rollback mechanisms.

Authors: Chan, Carven Schwartz-Narbonne, Daniel Sethi, Divjyot et al.

Source: DAC Design Automation Conference 2012; 1/ 1/2012, p1222-1228, 7p

Security Verification via Automatic Hardware-Aware Exploit Synthesis: The CheckMate Approach.

Authors: Trippel, Caroline Lustig, Daniel Martonosi, Margaret

Source: IEEE Micro; May-Jun2019, Vol. 39 Issue 3, p84-93, 10p

Subject Terms: HARDWARE, MATHEMATICAL combinations

Inferno: Streamlining Verification With Inferred Semantics.

Authors: DeOrio, Andrew Bauserman, Adam B. Bertacco, Valeria et al.

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; May2009, Vol. 28 Issue 5, p728-741, 14p

Subject Terms: COMPUTER hardware description languages, COMPUTER engineering -- Computer-aided design, COMPUTER logic, COMPUTER programming, DEBUGGING, COMPUTER software correctness, COMPUTER software testing