Výsledky vyhledávání - acm: b.: hardware/b.6: logic design/b.6.3: design _/b.6.3.0: automatizace synthesis*

ARMHEx: A hardware extension for DIFT on ARM-based SoCs

Autoři: Wahab, Muhammad Abdul Cotret, Pascal Nasr Allah, Mounir a další

Přispěvatelé: Wahab, Muhammad Abdul Cotret, Pascal Nasr Allah, Mounir a další

Zdroj: 2017 27th International Conference on Field Programmable Logic and Applications (FPL)
https://hal.science/hal-01558473
2017 27th International Conference on Field Programmable Logic and Applications (FPL), Sep 2017, Ghent, Belgium. ⟨10.23919/fpl.2017.8056767⟩
https://www.fpl2017.org/

Témata: Information Flow Tracking, SoC, Zynq, Zynq SoC, CoreSight, ARM Debug components, IFT, Dynamic information flow tracking, DIFT, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.6: Security and Protection, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Geografické téma: Ghent, Belgium

Dostupnost: https://hal.science/hal-01558473
https://hal.science/hal-01558473v1/document
https://hal.science/hal-01558473v1/file/bare_conf.pdf
https://doi.org/10.23919/fpl.2017.8056767

A semiempirical model for wakeup time estimation in power-gated logic clusters

Autoři: Tovinakere Dwarakanath, Vivek Sentieys, Olivier Derrien, Steven a další

Přispěvatelé: Tovinakere Dwarakanath, Vivek Sentieys, Olivier Derrien, Steven a další

Zdroj: The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012 ; https://inria.hal.science/hal-00752606 ; The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012, Jun 2012, San Fransisco, United States. pp.48-55

Témata: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.7: VLSI (very large scale integration), ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Geografické téma: San Fransisco, United States

Dostupnost: https://inria.hal.science/hal-00752606

N2S3, an Open-Source Scalable Spiking Neuromorphic Hardware Simulator

Autoři: Boulet, Pierre Devienne, Philippe Falez, Pierre a další

Přispěvatelé: Boulet, Pierre Devienne, Philippe Falez, Pierre a další

Zdroj: https://hal.science/hal-01432133 ; [Research Report] Université de Lille 1, Sciences et Technologies; CRIStAL UMR 9189. 2017.

Témata: simulation, neuromorphic architecture, SNN, SPiking neural networks, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.3: Simulation, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.7: Neural nets, [INFO.INFO-NE]Computer Science [cs]/Neural and Evolutionary Computing [cs.NE], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ET]Computer Science [cs]/Emerging Technologies [cs.ET], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

Dostupnost: https://hal.science/hal-01432133
https://hal.science/hal-01432133v2/document
https://hal.science/hal-01432133v2/file/n2s3.pdf

Analysis of Energy-Delay-Product for a 3D Vertical Nanowire FET Technology for Logic Applications

Autoři: O'Connor, Ian Stanojevic, Zlatan Baumgartner, Oskar a další

Přispěvatelé: O'Connor, Ian Stanojevic, Zlatan Baumgartner, Oskar a další

Zdroj: https://hal.science/hal-02732902 ; 2020.

Témata: ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics

Dostupnost: https://hal.science/hal-02732902
https://hal.science/hal-02732902v1/document
https://hal.science/hal-02732902v1/file/LEGO4TALK_EDP_Calculations.pdf

Soft timing closure for soft programmable logic cores: The ARGen approach

Autoři: Bollengier, Théotime Lagadec, Loïc Najem, Mohamad a další

Přispěvatelé: Bollengier, Théotime Lagadec, Loïc Najem, Mohamad a další

Zdroj: ARC 2017 - 13th International Symposium on Applied Reconfigurable Computing ; https://hal.science/hal-01475251 ; ARC 2017 - 13th International Symposium on Applied Reconfigurable Computing, Delft University of Technology Apr 2017, Delft, Netherlands ; http://www.arc2017.tudelft.nl

Témata: Reconfigurable cores, ACM: B.: Hardware, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.1: Design, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.2: Gate arrays, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.7: VLSI (very large scale integration), ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.11: Software Architectures/D.2.11.4: Patterns (e.g., client/server, pipeline, blackboard), [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Geografické téma: Delft, Netherlands

Dostupnost: https://hal.science/hal-01475251
https://hal.science/hal-01475251v1/document
https://hal.science/hal-01475251v1/file/paper_6-4.pdf

Digital Systems Design

Autoři: Sameni, Reza Shiraz University (Shiraz University)

Přispěvatelé: Sameni, Reza Shiraz University (Shiraz University)

Zdroj: https://hal.science/cel-01815308 ; Engineering school. Iran. 2018.

Témata: ACM: C.: Computer Systems Organization, ACM: B.: Hardware, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.1: Design, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-LO]Computer Science [cs]/Logic in Computer Science [cs.LO]

Dostupnost: https://hal.science/cel-01815308
https://hal.science/cel-01815308v1/document
https://hal.science/cel-01815308v1/file/CourseSlides2018.pdf

Throughput and FIFO Sizing: an Application to Latency-Insensitive Design

Autoři: Boucaron, Julien Coadou, Anthony de Simone, Robert a další

Přispěvatelé: Boucaron, Julien Coadou, Anthony de Simone, Robert a další

Zdroj: https://inria.hal.science/inria-00381644 ; [Research Report] RR-6919, INRIA. 2009, pp.19.

Témata: FIFO sizing, Buffer sizing, Throughput, Latency-Insensitive Design, Marked Graphs, ACM: F.: Theory of Computation/F.1: COMPUTATION BY ABSTRACT DEVICES/F.1.1: Models of Computation, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS, [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Dostupnost: https://inria.hal.science/inria-00381644
https://inria.hal.science/inria-00381644v1/document
https://inria.hal.science/inria-00381644v1/file/RR-6919.pdf

A Polynomial Based Approach to Wakeup Time and Energy Estimation in Power-Gated Logic Clusters

Autoři: D. Tovinakere, Vivek Sentieys, Olivier Derrien, Steven a další

Přispěvatelé: D. Tovinakere, Vivek Sentieys, Olivier Derrien, Steven a další

Zdroj: ISSN: 1546-1998 ; Journal of Low Power Electronics ; https://inria.hal.science/hal-00747721 ; Journal of Low Power Electronics, 2011, 7 (4), pp.482-489. ⟨10.1166/jolpe.2011.1159⟩.

Témata: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.2: Design Aids, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Dostupnost: https://inria.hal.science/hal-00747721
https://doi.org/10.1166/jolpe.2011.1159

Contributions to Program Optimization and High-Level Synthesis ; Contributions à l'optimisation de programmes et à la synthèse de circuits haut-niveau

Autoři: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Centre Inria de l'Université Grenoble Alpes a další

Přispěvatelé: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Centre Inria de l'Université Grenoble Alpes a další

Zdroj: https://inria.hal.science/tel-02151877 ; Hardware Architecture [cs.AR]. ENS de Lyon, 2019.

Témata: High-Level Synthesis, Compilation Techniques, Automatic Parallelization, Compilation, Parallélisation automatique, Synthèse haut-niveau, FPGA, ACM: B.: Hardware, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL]

Dostupnost: https://inria.hal.science/tel-02151877
https://inria.hal.science/tel-02151877v2/document
https://inria.hal.science/tel-02151877v2/file/hdr-alias.pdf

Model Driven Engineering Benefits for High Level Synthesis

Autoři: Le Beux, Sébastien Marquet, Philippe Dekeyser, Jean-Luc a další

Přispěvatelé: Le Beux, Sébastien Marquet, Philippe Dekeyser, Jean-Luc a další

Zdroj: https://inria.hal.science/inria-00311300 ; [Research Report] RR-6615, INRIA. 2008, pp.46.

Témata: ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.1: Design Styles/B.6.1.5: Parallel circuits, ACM: B.: Hardware/B.8: PERFORMANCE AND RELIABILITY/B.8.2: Performance Analysis and Design Aids, ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.5: Model Development/I.6.5.0: Modeling methodologies, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS/C.3.2: Real-time and embedded systems, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Dostupnost: https://inria.hal.science/inria-00311300
https://inria.hal.science/inria-00311300/document
https://inria.hal.science/inria-00311300/file/RR-6615.pdf

FPGA-Specific Synthesis of Loop-Nests with Pipelined Computational Cores

Autoři: Alias, Christophe Pasca, Bogdan Plesco, Alexandru a další

Přispěvatelé: Alias, Christophe Pasca, Bogdan Plesco, Alexandru a další

Zdroj: https://inria.hal.science/inria-00606977 ; [Research Report] RR-7674, INRIA. 2011, pp.33.

Témata: High-Level Synthesis, Compiler, ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES/B.2.4: High-Speed Arithmetic, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS/C.3.3: Signal processing systems, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL], [INFO.INFO-IA]Computer Science [cs]/Computer Aided Engineering, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Dostupnost: https://inria.hal.science/inria-00606977
https://inria.hal.science/inria-00606977v1/document
https://inria.hal.science/inria-00606977v1/file/RR-7674.pdf

Novel Architecture of Smart FFT Processor

Autoři: Teymourzadeh, Rozita University of California San Francisco (UC San Francisco) University of California (UC)

Přispěvatelé: Teymourzadeh, Rozita University of California San Francisco (UC San Francisco) University of California (UC)

Zdroj: https://hal.archives-ouvertes.fr/hal-01802071 ; 2014.

Témata: FFT, Digital Design, Processor, VLSI, Novel Architecture, Radix, Harmonic, ACM: D.: Software, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, ACM: I.: Computing Methodologies, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES, [INFO]Computer Science [cs], [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, [SPI]Engineering Sciences [physics], [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [SPI.TRON]Engineering Sciences [physics]/Electronics

Relation: hal-01802071; https://hal.archives-ouvertes.fr/hal-01802071; https://hal.archives-ouvertes.fr/hal-01802071/document; https://hal.archives-ouvertes.fr/hal-01802071/file/Novel%20Architecture%20of%20Smart%20FFT%20Processor_Draft.pdf

Dostupnost: https://hal.archives-ouvertes.fr/hal-01802071
https://hal.archives-ouvertes.fr/hal-01802071/document
https://hal.archives-ouvertes.fr/hal-01802071/file/Novel%20Architecture%20of%20Smart%20FFT%20Processor_Draft.pdf

Towards a hardware-assisted information flow tracking ecosystem for ARM processors

Autoři: Abdul Wahab, Muhammad Cotret, Pascal Nasr Allah, Mounir a další

Přispěvatelé: Abdul Wahab, Muhammad Cotret, Pascal Nasr Allah, Mounir a další

Zdroj: 26th International Conference on Field-Programmable Logic and Applications (FPL 2016)
https://hal.science/hal-01337579
26th International Conference on Field-Programmable Logic and Applications (FPL 2016), Aug 2016, Lausanne, Switzerland. ⟨10.1109/fpl.2016.7577396⟩
http://www.fpl2016.org

Témata: Heterogeneous SoC, DIFT, ARM Coresight components, Information Flow Tracking, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.7: VLSI (very large scale integration), ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.5: Heterogeneous (hybrid) systems, [SPI.TRON]Engineering Sciences [physics]/Electronics, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR]

Geografické téma: Lausanne, Switzerland

Dostupnost: https://hal.science/hal-01337579
https://hal.science/hal-01337579v1/document
https://hal.science/hal-01337579v1/file/fpl2016.pdf
https://doi.org/10.1109/fpl.2016.7577396

MixLock: Securing Mixed-Signal Circuits via Logic Locking

Autoři: Leonhard, Julian Yasin, Muhammad Turk, Shadi a další

Přispěvatelé: Leonhard, Julian Yasin, Muhammad Turk, Shadi a další

Zdroj: Design, Automation and Test in Europe (DATE 2019) ; https://hal.sorbonne-universite.fr/hal-02094516 ; Design, Automation and Test in Europe (DATE 2019), Mar 2019, Florence, Italy. pp.84-89

Témata: ACM: B.: Hardware, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [SPI.TRON]Engineering Sciences [physics]/Electronics, [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR]

Geografické téma: Florence, Italy

Time: Florence, Italy

Dostupnost: https://hal.sorbonne-universite.fr/hal-02094516
https://hal.sorbonne-universite.fr/hal-02094516v1/document
https://hal.sorbonne-universite.fr/hal-02094516v1/file/212_OutputPaper.pdf

La réalisation des opérateurs logiques

Autoři: Etiemble, Daniel Laboratoire de Recherche en Informatique (LRI) Université Paris-Sud - Paris 11 (UP11)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)

Přispěvatelé: Etiemble, Daniel Laboratoire de Recherche en Informatique (LRI) Université Paris-Sud - Paris 11 (UP11)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)

Zdroj: ISSN: 1776-0860 ; Techniques de l'Ingénieur ; https://hal.science/hal-01793651 ; 2017.

Témata: mémoires RAM, technologies CMOS, circuits CMOS | circuits ASIC, puissance et énergie, ACM: B.: Hardware, ACM: B.: Hardware/B.6: LOGIC DESIGN, [INFO]Computer Science [cs], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Dostupnost: https://hal.science/hal-01793651

Smart Vision Chip for colon exploration ; Smart Vision Chip pour l’exploration du colon

Autoři: Chuquimia, Orlando Systèmes Electroniques (SYEL) LIP6 a další

Přispěvatelé: Chuquimia, Orlando Systèmes Electroniques (SYEL) LIP6 a další

Zdroj: https://tel.archives-ouvertes.fr/tel-02494557 ; Imagerie médicale. Sorbonne Université, 2019. Français.

Témata: Automatic polyp detection, intelligent endoscopic capsule, Hough transform, fuzzy trees, fuzzy forest, artificial vision and hardware accelerator, vision artificielle et accélérateur matériel, Détection automatique des polypes, capsule endoscopique intelligente, transformée d’Hough, arbres flous, forets floues, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: C.: Computer Systems Organization/C.5: COMPUTER SYSTEM IMPLEMENTATION, ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE/I.2.6: Learning, ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE/I.2.9: Robotics, ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE/I.2.10: Vision and Scene Understanding, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.7: Feature Measurement/I.4.7.5: Texture, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.0: General/I.4.0.1: Image processing software, [INFO.INFO-IM]Computer Science [cs]/Medical Imaging, [INFO.INFO-CV]Computer Science [cs]/Computer Vision and Pattern Recognition [cs.CV], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI], [INFO.INFO-RB]Computer Science [cs]/Robotics [cs.RO]

Relation: tel-02494557; https://tel.archives-ouvertes.fr/tel-02494557; https://tel.archives-ouvertes.fr/tel-02494557/document; https://tel.archives-ouvertes.fr/tel-02494557/file/thhese_archivage__N%C2%B0dossier.pdf

Dostupnost: https://tel.archives-ouvertes.fr/tel-02494557
https://tel.archives-ouvertes.fr/tel-02494557/document
https://tel.archives-ouvertes.fr/tel-02494557/file/thhese_archivage__N%C2%B0dossier.pdf

Dynamic Variable Stage Pipeline: an Implementation of its Control

Autoři: Boucaron, Julien Coadou, Anthony Models and methods of analysis and optimization for systems with real-time and embedding constraints (AOSTE) a další

Přispěvatelé: Boucaron, Julien Coadou, Anthony Models and methods of analysis and optimization for systems with real-time and embedding constraints (AOSTE) a další

Zdroj: https://inria.hal.science/inria-00381563 ; [Research Report] RR-6918, INRIA. 2009, pp.15.

Témata: Variable length pipeline, Variable stage pipeline, Pipeline stage unification, Low Power, Leakage, Energy, Throughput, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Dostupnost: https://inria.hal.science/inria-00381563
https://inria.hal.science/inria-00381563v1/document
https://inria.hal.science/inria-00381563v1/file/RR-6918.pdf

Leveraging Power Spectral Density for Scalable System-Level Accuracy Evaluation

Autoři: Barrois, Benjamin Parashar, Karthick Sentieys, Olivier a další

Přispěvatelé: Barrois, Benjamin Parashar, Karthick Sentieys, Olivier a další

Zdroj: IEEE/ACM Conference on Design Automation and Test in Europe (DATE) ; https://inria.hal.science/hal-01253494 ; IEEE/ACM Conference on Design Automation and Test in Europe (DATE), Mar 2016, Dresden, Germany. pp.6

Témata: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES, ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING, ACM: B.: Hardware, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Geografické téma: Dresden, Germany

Relation: info:eu-repo/grantAgreement//287733/EU/Architecture oriented paraLlelization for high performance embedded Multicore systems using scilAb/ALMA

Dostupnost: https://inria.hal.science/hal-01253494
https://inria.hal.science/hal-01253494v1/document
https://inria.hal.science/hal-01253494v1/file/204_OutputPaper.pdf

MEMOCODE '21: Proceedings of the 19th ACM-IEEE International Conference on Formal Methods and Models for System Design

Autoři: S, Arunkumar Méry, Dominique Saha, Indranil a další

Přispěvatelé: S, Arunkumar Méry, Dominique Saha, Indranil a další

Témata: [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-LO] Computer Science [cs]/Logic in Computer Science [cs.LO], [INFO.INFO-SE] Computer Science [cs]/Software Engineering [cs.SE], [INFO.INFO-DS] Computer Science [cs]/Data Structures and Algorithms [cs.DS], [INFO.INFO-FL] Computer Science [cs]/Formal Languages and Automata Theory [cs.FL]

Přístupová URL adresa: https://inria.hal.science/hal-03529572v1
https://doi.org/10.1145/3487212

Design of Logically Obfuscated Memory and Arithmetic Logic Unit for Improved Hardware Security.

Autoři: Usharani, M. Sakthivel, B. Jayaram, K. a další

Zdroj: Intelligent Automation & Soft Computing; 2022, Vol. 33 Issue 3, p1665-1675, 11p

Témata: MEMORY, ARITHMETIC, REVERSE engineering, HARDWARE, LOGIC