Search Results - acm: b.: hardware/b.6: logic design/b.6.1: design style/b.6.1.5: parallel circuits~

Contributions to Program Optimization and High-Level Synthesis ; Contributions à l'optimisation de programmes et à la synthèse de circuits haut-niveau

Authors: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Centre Inria de l'Université Grenoble Alpes et al.

Contributors: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Centre Inria de l'Université Grenoble Alpes et al.

Source: https://inria.hal.science/tel-02151877 ; Hardware Architecture [cs.AR]. ENS de Lyon, 2019.

Subject Terms: High-Level Synthesis, Compilation Techniques, Automatic Parallelization, Compilation, Parallélisation automatique, Synthèse haut-niveau, FPGA, ACM: B.: Hardware, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL]

Availability: https://inria.hal.science/tel-02151877
https://inria.hal.science/tel-02151877v2/document
https://inria.hal.science/tel-02151877v2/file/hdr-alias.pdf

Design of High-Speed Logic Circuits with Four-Step RRAM-Based Logic Gates.

Authors: Cui, Xiaole Ma, Xiao Lin, Qiujun et al.

Source: Circuits, Systems & Signal Processing; Jun2020, Vol. 39 Issue 6, p2822-2840, 19p

Subject Terms: SEQUENTIAL circuits, COMBINATIONAL circuits, LOGIC circuit design, PARALLEL electric circuits, LOGIC circuits

The Ubimus Plugging Framework: Deploying FPGA-Based Prototypes for Ubiquitous Music Hardware Design.

Authors: Keller, Damián Jagwani, Aman Lazzarini, Victor

Source: Computers (2073-431X); Apr2025, Vol. 14 Issue 4, p155, 24p

Subject Terms: COMPUTER hardware description languages, LEARNING curve, GATE array circuits, LOGIC circuits, INTEGRATED circuits

Polymorphic Hybrid CMOS-MTJ Logic Gates for Hardware Security Applications.

Authors: Kumar, Rajat Divyanshu, Divyanshu Khan, Danial et al.

Source: Electronics (2079-9292); Feb2023, Vol. 12 Issue 4, p902, 14p

Subject Terms: MAGNETIC tunnelling, COMPLEMENTARY metal oxide semiconductors, LOGIC circuits, MAGNETIC devices, HARDWARE

Company/Entity: TAIWAN Semiconductor Manufacturing Co. Ltd.

Model Driven Engineering Benefits for High Level Synthesis

Authors: Le Beux, Sébastien Marquet, Philippe Dekeyser, Jean-Luc et al.

Contributors: Le Beux, Sébastien Marquet, Philippe Dekeyser, Jean-Luc et al.

Source: https://inria.hal.science/inria-00311300 ; [Research Report] RR-6615, INRIA. 2008, pp.46.

Subject Terms: ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.1: Design Styles/B.6.1.5: Parallel circuits, ACM: B.: Hardware/B.8: PERFORMANCE AND RELIABILITY/B.8.2: Performance Analysis and Design Aids, ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.5: Model Development/I.6.5.0: Modeling methodologies, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS/C.3.2: Real-time and embedded systems, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Availability: https://inria.hal.science/inria-00311300
https://inria.hal.science/inria-00311300/document
https://inria.hal.science/inria-00311300/file/RR-6615.pdf

Reinforcement-Learning-Based Synthesis of Custom Approximate Parallel Prefix Adders.

Authors: Stefanidis, Apostolos Dimitrakopoulos, Giorgos

Source: Journal of Low Power Electronics & Applications; Dec2024, Vol. 14 Issue 4, p57, 25p

Subject Terms: REINFORCEMENT learning, LOGIC circuits, ENERGY consumption, TRANSISTORS, SUFFIXES & prefixes (Grammar)

A Hardware Trojan Detection and Diagnosis Method for Gate-Level Netlists Based on Machine Learning and Graph Theory.

Authors: Wang, Junjie Zhai, Guangxi Gao, Hongxu et al.

Source: Electronics (2079-9292); Jan2024, Vol. 13 Issue 1, p59, 20p

Subject Terms: DIAGNOSIS, MACHINE learning, PARALLEL algorithms, INTEGRATED circuits, HARDWARE

Efficient Design of Reversible Adder and Multiplier Using Peres Gates.

Authors: Kadbe, Premanand K. Markande, Shriram D.

Source: Applied Sciences (2076-3417); Oct2024, Vol. 14 Issue 20, p9385, 24p

Subject Terms: LOGIC circuits, LOGIC, ACHIEVEMENT

Parallel Algorithms Development for Programmable Devices with Application from Cryptography.

Authors: Damaj, Issam

Source: International Journal of Parallel Programming; Dec2007, Vol. 35 Issue 6, p529-572, 44p, 16 Diagrams, 4 Charts

Subject Terms: FIELD programmable gate arrays, COMPUTER programming, PARALLEL algorithms, PROGRAMMING languages, GATE array circuits, PROGRAMMABLE logic devices, CRYPTOGRAPHY

Incremental SAT-Based Reverse Engineering of Camouflaged Logic Circuits.

Authors: Yu, Cunxi Zhang, Xiangyu Liu, Duo et al.

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Oct2017, Vol. 36 Issue 10, p1647-1659, 13p

Subject Terms: LOGIC circuits, REVERSE engineering, COMBINATIONAL circuits, ALGORITHMS, INTEGRATED circuit design

Co-Design of Multicore Hardware and Multithreaded Software for Thread Performance Assessment on an FPGA.

Authors: Adam, George K.

Source: Computers (2073-431X); May2022, Vol. 11 Issue 5, p76-N.PAG, 13p

Subject Terms: GATE array circuits, COMPUTER systems, PARTICIPATORY design, MULTICORE processors, INTERNET of things

Generating Direct Logic Circuit Implementations of Deeply Quantized Neural Networks Using Chisel4ml.

Authors: Vreča, Jure Biasizzo, Anton

Source: Electronics (2079-9292); Mar2025, Vol. 14 Issue 5, p849, 21p

Subject Terms: POLYNOMIAL time algorithms, MACHINE learning, LOGIC circuits, TIME management

A Scalable Formal Framework for the Verification and Vulnerability Analysis of Redundancy-Based Error-Resilient Null Convention Logic Asynchronous Circuits.

Authors: Mazumder, Dipayan Datta, Mithun Bodoh, Alexander C. et al.

Source: Journal of Low Power Electronics & Applications; Mar2024, Vol. 14 Issue 1, p5, 24p

Subject Terms: ASYNCHRONOUS circuits, LOGIC circuits, SOFT errors, CIRCUIT complexity, ELECTROMAGNETIC interference

N2S3, an Open-Source Scalable Spiking Neuromorphic Hardware Simulator

Authors: Boulet, Pierre Devienne, Philippe Falez, Pierre et al.

Contributors: Boulet, Pierre Devienne, Philippe Falez, Pierre et al.

Source: https://hal.science/hal-01432133 ; [Research Report] Université de Lille 1, Sciences et Technologies; CRIStAL UMR 9189. 2017.

Subject Terms: simulation, neuromorphic architecture, SNN, SPiking neural networks, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.3: Simulation, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.7: Neural nets, [INFO.INFO-NE]Computer Science [cs]/Neural and Evolutionary Computing [cs.NE], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ET]Computer Science [cs]/Emerging Technologies [cs.ET], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

Availability: https://hal.science/hal-01432133
https://hal.science/hal-01432133v2/document
https://hal.science/hal-01432133v2/file/n2s3.pdf

Accuracy Analysis on Design of Stochastic Computing in Arithmetic Components and Combinational Circuit.

Authors: Ashok, P. Bala Tripura Sundari, B.

Source: Computation; Dec2023, Vol. 11 Issue 12, p237, 15p

Subject Terms: COMBINATIONAL circuits, STOCHASTIC analysis, LOGIC circuits, STOCHASTIC systems, SHIFT registers, ALGEBRAIC equations

Applying Genetic Parallel Programming to Synthesize Combinational Logic Circuits.

Authors: Sin Man Cheang Kin Hong Lee Kwong Sak Leung

Source: IEEE Transactions on Evolutionary Computation; Aug2007, Vol. 11 Issue 4, p503-520, 18p

Subject Terms: EVOLUTIONARY computation, GENETIC programming, PARALLEL programming, DIGITAL electronics, LOGIC circuits, LOGIC design

Convolutional Neural Network Model Compression Method for Software—Hardware Co-Design.

Authors: Jang, Seojin Liu, Wei Cho, Yongbeom

Source: Information; Oct2022, Vol. 13 Issue 10, p451-N.PAG, 15p

Subject Terms: CONVOLUTIONAL neural networks, PARTICIPATORY design, GATE array circuits, COMPUTER software, PARALLEL processing, GRAPHICS processing units, SYSTEMS on a chip

A Novel Probability-Based Logic-Locking Technique: ProbLock.

Authors: Yue, Michael Tehranipoor, Sara

Source: Sensors (14248220); Dec2021, Vol. 21 Issue 23, p8126, 1p

Subject Terms: SEQUENTIAL circuits, INTEGRATED circuits, COMBINATIONAL circuits, ALGORITHMS, SECURITY systems, DESIGN techniques

CAPTIVE: Constrained Adversarial Perturbations to Thwart IC Reverse Engineering.

Authors: Zargari, Amir Hosein Afandizadeh AshrafiAmiri, Marzieh Seo, Minjun et al.

Source: Information; Dec2023, Vol. 14 Issue 12, p656, 15p

Subject Terms: REVERSE engineering, LOGIC circuits, ELECTRONIC design automation, INTEGRATED circuits, MACHINE learning, INTELLECTUAL property

Geographic Terms: CONGO (Democratic Republic)

Design and architecture for an embedded 32-bit QueueCore.

Authors: Abderazek, Ben A. Kawata, Sotaro Sowa, Masahiro

Source: Journal of Embedded Computing; 2006, Vol. 2 Issue 2, p191-205, 15p, 1 Black and White Photograph, 8 Diagrams, 2 Charts, 4 Graphs

Subject Terms: EMBEDDED computer systems, INTEGRATED circuits, COMPUTER architecture, MICROPROCESSORS, PROGRAMMABLE logic devices