Search Results - acm: b.: hardware/b.2: arithmetic AND (logic OR login) structures/b.2.4: high-speed arithmetic

Randomization of Arithmetic over Polynomial Modular Number System

Authors: Didier, Laurent-Stéphane Dosso, Fangan-Yssouf El Mrabet, Nadia et al.

Contributors: Didier, Laurent-Stéphane Dosso, Fangan-Yssouf El Mrabet, Nadia et al.

Source: 26th IEEE International Symposium on Computer Arithmetic
https://hal.science/hal-02099713
26th IEEE International Symposium on Computer Arithmetic, Jun 2019, Kyoto, Japan. pp.199-206, ⟨10.1109/ARITH.2019.00048⟩

Subject Terms: Polynomial Modular Number System, Side Channel Countermeasure, Modular Artithmetic, ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES/B.2.4: High-Speed Arithmetic/B.2.4.0: Algorithms, [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR], [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic

Subject Geographic: Kyoto, Japan

Time: Kyoto, Japan

Availability: https://hal.science/hal-02099713
https://hal.science/hal-02099713v1/document
https://hal.science/hal-02099713v1/file/Randomisation_of_Arithmeticover_Polynomial_Modular_Number_System-20.pdf
https://doi.org/10.1109/ARITH.2019.00048

Efficient modular operations using the adapted modular number system

Authors: Didier, Laurent-Stéphane Dosso, Fangan-Yssouf Véron, Pascal et al.

Contributors: Didier, Laurent-Stéphane Dosso, Fangan-Yssouf Véron, Pascal et al.

Source: ISSN: 2190-8508.

Subject Terms: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES/B.2.4: High-Speed Arithmetic, [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR]

Availability: https://hal.science/hal-02486345
https://hal.science/hal-02486345v1/document
https://hal.science/hal-02486345v1/file/amns_jcen-3.pdf
https://doi.org/10.1007/s13389-019-00221-7

On the Computation of Correctly-Rounded Sums

Authors: Kornerup, Peter Lefèvre, Vincent Louvet, Nicolas et al.

Contributors: Kornerup, Peter Lefèvre, Vincent Louvet, Nicolas et al.

Source: 19th IEEE Symposium on Computer Arithmetic - Arith'19
https://inria.hal.science/inria-00367584
19th IEEE Symposium on Computer Arithmetic - Arith'19, Jun 2009, Portland, Oregon, United States

Subject Terms: floating-point arithmetic, summation algorithms, correct rounding, 2Sum and Fast2Sum algorithms, ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES/B.2.4: High-Speed Arithmetic, ACM: G.: Mathematics of Computing/G.1: NUMERICAL ANALYSIS/G.1.0: General, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic

Subject Geographic: Portland, Oregon, United States

Availability: https://inria.hal.science/inria-00367584
https://inria.hal.science/inria-00367584v2/document
https://inria.hal.science/inria-00367584v2/file/arith19.pdf

RNS Modular Multiplication through Reduced Base Extensions

Authors: Bigou, Karim Tisserand, Arnaud Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources (CAIRN) et al.

Contributors: Bigou, Karim Tisserand, Arnaud Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources (CAIRN) et al.

Source: ASAP - 25th IEEE International Conference on Application-specific Systems, Architectures and Processors ; https://inria.hal.science/hal-01010961 ; ASAP - 25th IEEE International Conference on Application-specific Systems, Architectures and Processors, Jun 2014, Zurich, Switzerland. pp.57-62, ⟨10.1109/ASAP.2014.6868631⟩

Subject Terms: Residue Number System, Montgomery Multiplication, Finite Field Arithmetic, Asymmetric Cryptography, Elliptic Curve Cryptography (ECC), Discrete Logarithm (DL), ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES/B.2.4: High-Speed Arithmetic, ACM: E.: Data/E.3: DATA ENCRYPTION/E.3.2: Public key cryptosystems, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Subject Geographic: Zurich, Switzerland

Availability: https://inria.hal.science/hal-01010961
https://inria.hal.science/hal-01010961v1/document
https://inria.hal.science/hal-01010961v1/file/article_asap2014.pdf
https://doi.org/10.1109/ASAP.2014.6868631

Accelerated Shift-and-Add Algorithms: Accelerated shift-and-add algorithms

Authors: Revol, Nathalie Yakoubsohn, Jean-Claude Computer arithmetic (ARENAIRE) et al.

Contributors: Revol, Nathalie Yakoubsohn, Jean-Claude Computer arithmetic (ARENAIRE) et al.

Source: Reliable Computing. 6:193-205

Subject Terms: ACM: G.: Mathematics of Computing/G.1: NUMERICAL ANALYSIS/G.1.7: Ordinary Differential Equations, Computation of special functions and constants, construction of tables, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES/B.2.4: High-Speed Arithmetic, shift-and-add algorithms, [INFO.INFO-AO] Computer Science [cs]/Computer Arithmetic, Other functions coming from differential, difference and integral equations, Numerical methods for initial value problems involving ordinary differential equations, Special ordinary differential equations (Mathieu, Hill, Bessel, etc.)

File Description: application/xml

Access URL: https://link.springer.com/article/10.1023%2FA%3A1009921407000
https://hal.inria.fr/inria-00545004
https://dblp.uni-trier.de/db/journals/rc/rc6.html#RevolY00

Simultaneous floating-point sine and cosine for VLIW integer processors

Authors: Jeannerod, Claude-Pierre Jourdan-Lu, Jingyan Arithmetic and Computing (ARIC) et al.

Contributors: Jeannerod, Claude-Pierre Jourdan-Lu, Jingyan Arithmetic and Computing (ARIC) et al.

Source: 23rd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2012)
https://inria.hal.science/hal-00672327
23rd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2012), Jul 2012, Delft, Netherlands. pp.69-76

Subject Terms: VLIW integer processor, instruction level parallelism, C software implementation, floating-point arithmetic, IEEE 754, unit in the last place, trigonometric function, ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES/B.2.4: High-Speed Arithmetic, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.1: Single Data Stream Architectures/C.1.1.2: RISC/CISC, VLIW architectures, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Subject Geographic: Delft, Netherlands

Availability: https://inria.hal.science/hal-00672327
https://inria.hal.science/hal-00672327v1/document
https://inria.hal.science/hal-00672327v1/file/Jeannerod-JourdanLu.pdf

FPGA-Specific Synthesis of Loop-Nests with Pipelined Computational Cores

Authors: Alias, Christophe Pasca, Bogdan Plesco, Alexandru et al.

Contributors: Alias, Christophe Pasca, Bogdan Plesco, Alexandru et al.

Source: https://inria.hal.science/inria-00606977 ; [Research Report] RR-7674, INRIA. 2011, pp.33.

Subject Terms: High-Level Synthesis, Compiler, ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES/B.2.4: High-Speed Arithmetic, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS/C.3.3: Signal processing systems, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL], [INFO.INFO-IA]Computer Science [cs]/Computer Aided Engineering, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Availability: https://inria.hal.science/inria-00606977
https://inria.hal.science/inria-00606977v1/document
https://inria.hal.science/inria-00606977v1/file/RR-7674.pdf

Multi-operand Decimal Adder Trees for FPGAs

Authors: Vazquez, Alvaro de Dinechin, Florent Computer arithmetic (ARENAIRE) et al.

Contributors: Vazquez, Alvaro de Dinechin, Florent Computer arithmetic (ARENAIRE) et al.

Source: https://inria.hal.science/inria-00526327 ; [Research Report] RR-7420, INRIA. 2010, pp.20.

Subject Terms: Decimal arithmetic, IEEE 754-2008, BCD multi-operand addition, carry-ripple adder, pipelined adder trees, FPGA implementation, ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES/B.2.4: High-Speed Arithmetic, ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES/B.2.0: General, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic

Availability: https://inria.hal.science/inria-00526327
https://inria.hal.science/inria-00526327v1/document
https://inria.hal.science/inria-00526327v1/file/RR-7420.pdf

Code generation for argument filtering and argument reduction in elementary functions

Authors: de Dinechin, Florent Jeannerod, Claude-Pierre Pfannholzer, David et al.

Contributors: de Dinechin, Florent Jeannerod, Claude-Pierre Pfannholzer, David et al.

Source: SCAN 2010: 14th GAMM-IMACS International Symposium on Scientific Computing, Computer Arithmetic and Validated Numerics ; https://inria.hal.science/inria-00544808 ; SCAN 2010: 14th GAMM-IMACS International Symposium on Scientific Computing, Computer Arithmetic and Validated Numerics, Revol, Nathalie and de Dinechin, Florent and Jeannerod, Claude-Pierre and Lefèvre, Vincent and Louvet, Nicolas and Morin, Sèverine and Nguyen, Hong Diep, Sep 2010, Lyon, France

Subject Terms: scientific computing, computer arithmetic, validated numerics, ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES/B.2.4: High-Speed Arithmetic, ACM: G.: Mathematics of Computing/G.4: MATHEMATICAL SOFTWARE, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic

Subject Geographic: Lyon, France

Availability: https://inria.hal.science/inria-00544808

An efficient rounding boundary test for pow(x,y) in double precision

Authors: Lauter, Christoph Quirin Lefèvre, Vincent Computer arithmetic (ARENAIRE) et al.

Contributors: Lauter, Christoph Quirin Lefèvre, Vincent Computer arithmetic (ARENAIRE) et al.

Source: ISSN: 0018-9340 ; IEEE Transactions on Computers ; https://inria.hal.science/inria-00583988 ; IEEE Transactions on Computers, 2009, 58 (2), pp.197-207. ⟨10.1109/TC.2008.202⟩.

Subject Terms: floating-point arithmetic, correct rounding, power function, ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES/B.2.4: High-Speed Arithmetic, ACM: G.: Mathematics of Computing/G.1: NUMERICAL ANALYSIS/G.1.0: General/G.1.0.0: Computer arithmetic, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic

Availability: https://inria.hal.science/inria-00583988
https://doi.org/10.1109/TC.2008.202