Výsledky vyhledávání - VLSI-array processor architecture

Design Optimization of VLSI Array Processor Architecture for Window Image Processing.

Autoři: kunieda, hiroaki

Témata: Journal Article., NA.

URL: http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100405669

Design Optimization of VLSI Array Processor Architecture for Window Image Processing.

Autoři: LI, DONGJU

Témata: Journal Article., NA.

URL: http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100402899

Design Optimization of VLSI Array Processor Architecture for Window Image Processing

Zdroj: Design Optimization of VLSI Array Processor Architecture for Window Image Processing. (8):1475-1484

Design Optimization of VLSI Array Processor Architecture for Window Image Processing

Zdroj: Design Optimization of VLSI Array Processor Architecture for Window Image Processing. (8):1475-1484

A mathematical programming method for constructing the shortest interconnection VLSI arrays.

Autoři: Ding, Hao Qian, Junyan Zhao, Lingzhong a další

Zdroj: Integration: The VLSI Journal. Nov2021, Vol. 81, p167-174. 8p.

Témata: *ARRAY processors, *VERY large scale circuit integration, *INTEGER programming, *PARALLEL processing, *MATHEMATICAL programming

Basic hardware module for a nonlinear programming algorithm and applications

Autoři: Shin-Yeu Lin

Zdroj: Automatica. 33:1579-1586

Témata: 0209 industrial biotechnology, 02 engineering and technology, nonlinear system, Control/observation systems involving computers (process control, etc.), VLSI-array processor architecture, optimal control, 0203 mechanical engineering, Nonlinear programming, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), discrete-time optimization, nonlinear programming, Nonlinear systems in control theory, control constraints, hardware module

Popis souboru: application/xml

Přístupová URL adresa: https://www.sciencedirect.com/science/article/pii/S0005109897000538
https://ir.nctu.edu.tw:443/handle/11536/422
https://dblp.uni-trier.de/db/journals/automatica/automatica33.html#Lin97a
https://ir.nctu.edu.tw/bitstream/11536/422/1/A1997XU55600015.pdf

Design Optimization of VLSI Array Processor Architecture for Window Image Processing

Autoři: Dongju Li Li Jiang Hiroaki Kunieda

Relation: oai:t2r2.star.titech.ac.jp:00216915

Dostupnost: http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100405669

Design Optimization of VLSI Array Processor Architecture for Window Image Processing

Autoři: Dongju Li Li Jiang Hiroaki KUNIEDA a další

Přispěvatelé: Dongju Li Li Jiang Hiroaki KUNIEDA a další

Zdroj: http://search.ieice.org/1999/files/./pdf/e82-a_8_1475.pdf.

Popis souboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.29.7757

Dostupnost: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.29.7757
http://search.ieice.org/1999/files/./pdf/e82-a_8_1475.pdf

New VLSI Array Processor Design for Image Window Operations.

Autoři: Li, D.J. Jiang, L.

Zdroj: IEEE Transactions on Circuits & Systems Part II: Analog & Digital Signal Processing. May1999, Vol. 46 Issue 5, p635. 6p. 4 Diagrams, 4 Charts.

Témata: *ARRAY processors, *IMAGE processing, *DESIGN

VLSI Array Processor for Signal Processing.

Autoři: UNIVERSITY OF SOUTHERN CALIFORNIA LOS ANGELES DEPT OF ELECTRICAL ENGINEERING Kung,Sun-Yuan

Zdroj: DTIC AND NTIS

Témata: Computer Hardware, Non-radio Communications, SIGNAL PROCESSING, COMPUTER ARCHITECTURE, PARALLEL PROCESSORS, ALGORITHMS, TWO DIMENSIONAL, HIGH VELOCITY, MAXIMUM LIKELIHOOD ESTIMATION, ARRAYS, KALMAN FILTERING, PROCESSING EQUIPMENT, ADAPTIVE FILTERS, SPECTRUM ANALYSIS, VLSI(Very Large Scale Integration), Text

URL: https://apps.dtic.mil/docs/citations/ADA122078

A data-driven VLSI array for arbitrary algorithms

Přispěvatelé: Silberman, G [Carnegie-Mellon Univ. (US)]

Zdroj: Computer; (United States); 21:10

Popis souboru: Medium: X; Size: Pages: 30-44

Přístupová URL adresa: http://www.osti.gov/scitech/biblio/6432607

Processor Architecture

Autoři: Jurij Silc Borut Robic Theo Ungerer

Resource Type: eBook.

Témata: Microprocessors, Computer architecture, Architecture

Categories: COMPUTERS / Computer Architecture, ART / General

On Mapping Cube Graphs on VLSI Array and Tree Architectures.

Autoři: MARYLAND UNIV COLLEGE PARK CENTER FOR AUTOMATION RESEARCH Ramakrishnan,I V Varman,P J

Zdroj: DTIC AND NTIS

Témata: Electrical and Electronic Equipment, Theoretical Mathematics, Computer Hardware, Trees, Processing equipment, Graphs, Arrays, Integrated circuits, Computer architecture, Algorithms, Mapping, Circuit interconnections, Computations, Faults, Requirements, Models, Architecture, Global clocks, VLSI(Very Large Scale Integration), Rectangular arrays, Tree machines, Hexagonal arrays, Liner arrays, Cube graphs, Array algorithms, Pipelining, WUAFOSR2304A2, PE61102F, Text

URL: https://apps.dtic.mil/docs/citations/ADA139306

A programmable array processor architecture for flexible approximate string matching algorithms.

Autoři: Michailidis, P.D. Margaritis, K.G.

Zdroj: 2005 International Conference on Parallel Processing Workshops (ICPPW'05); 2005, p201-209, 9p

Multilevel simulation tool for designing fault-tolerant VLSI array processors

Autoři: Manfred Glesner G.K. Sharma P. Poechmueller

Zdroj: [1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design. :293-294

Přístupová URL adresa: http://ieeexplore.ieee.org/document/185139/
https://ieeexplore.ieee.org/document/185139/

Architecture and Operations of the VLSI Array Processors for Implementing a Receding Horizon Controller

Autoři: Shin-Yeu Lin

Zdroj: IFAC Proceedings Volumes. 28:789-794

Témata: 0209 industrial biotechnology, 0203 mechanical engineering, 02 engineering and technology

Přístupová URL adresa: https://www.sciencedirect.com/science/article/pii/S1474667017469254

A complete system for NN classification based on a VLSI array processor

Autoři: Roberto Guerrieri Alberto Ferrari Michele Borgatti

Zdroj: Pattern Recognition. 33:2083-2093

Témata: Computing methodologies and applications, pattern classification, Pattern recognition, speech recognition, configurable architecture, array processor, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, \(k\)-nearest neighbors, VLSI

Popis souboru: application/xml

Přístupová URL adresa: https://zbmath.org/1872241
https://doi.org/10.1016/s0031-3203(99)00192-2
http://www.sciencedirect.com/science/article/pii/S0031320399001922
https://www.sciencedirect.com/science/article/abs/pii/S0031320399001922
http://dblp.uni-trier.de/db/journals/pr/pr33.html#FerrariBG00
https://dblp.uni-trier.de/db/journals/pr/pr33.html#FerrariBG00
https://ui.adsabs.harvard.edu/abs/2000PatRe..33.2083F/abstract

Optimization of Number of Processors in VLSI Arrays

Autoři: Saouter, Yannick Inria, Rapport De Recherche

Přispěvatelé: Saouter, Yannick Inria, Rapport De Recherche

Témata: [INFO.INFO-OH] Computer Science [cs]/Other [cs.OH], NON-LINEAR OPTIMIZATION, HYPERVOLUME, AUTOMATIC DERIVATION OF PARALLEL ARCHITECTURES

Popis souboru: application/pdf

Přístupová URL adresa: https://inria.hal.science/inria-00074342v1

Area time trade-offs in micro-grain VLSI array architectures: Area time trade-offs in micro-grain VLSI array architectures.

Autoři: Robert Michael Owens Mary Jane Irwin R. Singh Bajwa

Zdroj: IEEE Transactions on Computers. 43:1121-1128

Témata: Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, Mathematical problems of computer architecture

Popis souboru: application/xml

Přístupová URL adresa: https://zbmath.org/1964130
https://doi.org/10.1109/12.324538
https://dblp.uni-trier.de/db/journals/tc/tc43.html#BajwaOI94
https://doi.org/10.1109/12.324538
https://pennstate.pure.elsevier.com/en/publications/area-time-trade-offs-in-micro-grain-vlsi-array-architectures
http://ieeexplore.ieee.org/document/324538/
https://ieeexplore.ieee.org/document/324538/

A VLSI array architecture with dynamic frequency clocking

Autoři: N. Bhavanishankar Nagarajan Ranganathan N. Vijaykrishnan

Zdroj: Proceedings International Conference on Computer Design. VLSI in Computers and Processors. :137-140

Témata: 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology

Přístupová URL adresa: http://doi.ieeecomputersociety.org/10.1109/ICCD.1996.563547
https://dblp.uni-trier.de/db/conf/iccd/iccd1996.html#RanganathanVB96
https://pennstate.pure.elsevier.com/en/publications/vlsi-array-architecture-with-dynamic-frequency-clocking
https://ieeexplore.ieee.org/document/563547/