Výsledky vyhledávání - Multiple Data Stream Architectures- MIMD Processors~

Single or multiple instruction-multiple data stream architecture (SIMD and MIMD). January 1983-May 1988 (Citations from the Computer data base). Report for January 1983-May 1988

Zdroj: Other Information: Supersedes PB--87-860367

Popis souboru: Medium: X; Size: Pages: 43

Přístupová URL adresa: http://www.osti.gov/scitech/biblio/7043355

FlexBulk: Intelligently Forming Atomic Blocks in Blocked-Execution Multiprocessors to Minimize Squashes

Autoři: Rishi Agarwal Josep Torrellas The Pennsylvania State University CiteSeerX Archives

Přispěvatelé: Rishi Agarwal Josep Torrellas The Pennsylvania State University CiteSeerX Archives

Zdroj: http://iacoma.cs.uiuc.edu/iacoma-papers/isca11_1.pdf.

Témata: Categories and Subject Descriptors C.1.2 [Processor Architectures, Multiple Data Stream Architectures- MIMD Processors, D.1.3 [Programming Techniques, Concurrent Programming- Parallel Programming. General Terms Design, Performance. Keywords Atomic Block Execution, Thread Squash, Speculation

Popis souboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.307.5609

Dostupnost: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.307.5609
http://iacoma.cs.uiuc.edu/iacoma-papers/isca11_1.pdf

QuickRec: Prototyping an Intel Architecture Extension for Record and Replay of Multithreaded Programs ∗

Autoři: Gilles Pokam Klaus Danne Cristiano Pereira a další

Přispěvatelé: Gilles Pokam Klaus Danne Cristiano Pereira a další

Zdroj: http://iacoma.cs.uiuc.edu/iacoma-papers/isca13_1.pdf.

Témata: Categories and Subject Descriptors C.1.2 [Processor Architectures, Multiple Data Stream Architectures (Multiprocessors)- MIMD Processors, C.4 [Performance of Systems, Design Studies, C.0 [General, Hardware/software interfaces Keywords Deterministic Record and Replay, Shared Memory Multiprocessors, Hardware-Software Interface, FPGA Prototype

Popis souboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.307.3183

Dostupnost: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.307.3183
http://iacoma.cs.uiuc.edu/iacoma-papers/isca13_1.pdf

Static scheduling for barrier MIMD architectures.

Autoři: Dietz, Henry Zaafrani, Abderrazek O'Keefe, Matthew

Zdroj: Journal of Supercomputing; Feb1992, Vol. 5 Issue 4, p263-289, 27p

RelaxReplay: Record and Replay for Relaxed-Consistency Multiprocessors

Autoři: Nima Honarm Josep Torrellas The Pennsylvania State University CiteSeerX Archives

Přispěvatelé: Nima Honarm Josep Torrellas The Pennsylvania State University CiteSeerX Archives

Zdroj: http://iacoma.cs.uiuc.edu/iacoma-papers/asplos14.pdf.

Témata: Categories and Subject Descriptors C.1.2 [Processor Ar- chitectures, Multiple Data Stream Architectures (Multipro- cessors)- MIMD Processors, D.1.3 [Programming Tech- niques, Concurrent Programming- Parallel Programming Keywords Memory Race Recording, Record and Determin- istic Replay, Relaxed Consistency

Popis souboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.649.4678

Dostupnost: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.649.4678
http://iacoma.cs.uiuc.edu/iacoma-papers/asplos14.pdf

Supporting Runtime Reconfigurable VLIWs Cores Through Dynamic Binary Translation

Autoři: Rokicki, Simon Rohou, Erven Derrien, Steven a další

Přispěvatelé: Rokicki, Simon Rohou, Erven Derrien, Steven a další

Zdroj: DATE 2018 - IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition ; https://hal.science/hal-01653110 ; DATE 2018 - IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition, Mar 2018, Dresden, Germany. pp.1009-1014, ⟨10.23919/DATE.2018.8342160⟩ ; https://www.date-conference.com

Témata: ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.5: Heterogeneous (hybrid) systems, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.0: Adaptable architectures, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.2: Multiple Data Stream Architectures (Multiprocessors)/C.1.2.4: Multiple-instruction-stream, multiple-data-stream processors (MIMD), ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.0: Code generation, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Geografické téma: Dresden, Germany

Dostupnost: https://hal.science/hal-01653110
https://hal.science/hal-01653110v2/document
https://hal.science/hal-01653110v2/file/rokicki_18_hal.pdf
https://doi.org/10.23919/DATE.2018.8342160

Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture.

Autoři: Kim, Yoonjin Mahapatra, Rabi N. Park, Ilhyun a další

Zdroj: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; May2009, Vol. 17 Issue 5, p593-603, 11p, 4 Black and White Photographs, 14 Diagrams, 4 Charts

Témata: COMPUTER architecture, CACHE memory, EMBEDDED computer systems, INTELLECTUAL property, DATA pipelining, POWER (Mechanics)

Hardware-Accelerated Dynamic Binary Translation

Autoři: Rokicki, Simon Rohou, Erven Derrien, Steven a další

Přispěvatelé: Rokicki, Simon Rohou, Erven Derrien, Steven a další

Zdroj: IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition (DATE) ; https://inria.hal.science/hal-01423639 ; IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar 2017, Lausanne, Switzerland ; https://www.date-conference.com/

Témata: ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.5: Heterogeneous (hybrid) systems, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.0: Adaptable architectures, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.2: Multiple Data Stream Architectures (Multiprocessors)/C.1.2.4: Multiple-instruction-stream, multiple-data-stream processors (MIMD), ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.0: Code generation, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Geografické téma: Lausanne, Switzerland

Dostupnost: https://inria.hal.science/hal-01423639
https://inria.hal.science/hal-01423639v1/document
https://inria.hal.science/hal-01423639v1/file/rokicki_DATE_cr.pdf

Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators

Autoři: Yunsup Lee Rimas Avizienis Alex Bishara a další

Přispěvatelé: Yunsup Lee Rimas Avizienis Alex Bishara a další

Zdroj: http://cseweb.ucsd.edu/~marora/cse290/sp11/papers/batten2011.pdf.

Témata: Categories and Subject Descriptors C.1.2 [Processor Architectures, Multiple Data Stream Architectures—array and vector processors, MIMD, SIMD General Terms

Popis souboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.393.744; http://cseweb.ucsd.edu/~marora/cse290/sp11/papers/batten2011.pdf

Dostupnost: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.393.744
http://cseweb.ucsd.edu/~marora/cse290/sp11/papers/batten2011.pdf

Parallel processing computer containing a multiple instruction stream processing architecture

Compiling for Shared-Memory and Message-Passing

Autoři: James R. Larus The Pennsylvania State University CiteSeerX Archives

Přispěvatelé: James R. Larus The Pennsylvania State University CiteSeerX Archives

Zdroj: http://ftp.cs.wisc.edu/wwt/hw_sw_sm.pdf.

Témata: Categories and Subject Descriptors, B.3.2, Memory Structures, Design Styles—shared memory, C.1.2, Processor Architectures, Multiple Data Stream Architectures (Multiprocessors)—multiple-instruction-stream, multipledata-stream (MIMD, parallel processors, D.1.3, Programming Techniques, Concurrent programming—parallel programming, D.3.4 [Programming Languages, Processors—compilers, optimization, run-time environments. General Terms, Languages, performance. Additional Key Words and Phrases, Compilers, parallel programming languages, shared-memory

Popis souboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.414.8743; http://ftp.cs.wisc.edu/wwt/hw_sw_sm.pdf

Dostupnost: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.414.8743
http://ftp.cs.wisc.edu/wwt/hw_sw_sm.pdf

Optimal Evaluation of Array Expressions on Massively Parallel Machines

Autoři: Siddhartha Chatterjee John R. Gilbert Robert Schreiber a další

Přispěvatelé: Siddhartha Chatterjee John R. Gilbert Robert Schreiber a další

Zdroj: ftp://ftp.cs.unc.edu/pub/users/sc/papers/toplas-cdp.pdf

Témata: Categories and Subject Descriptors, C.1.2 [Processor Architectures, Multiple Data Stream Architectures (Multiprocessors)|interconnection networks, SIMD, MIMD, D.3.4 [Programming Languages, Processors|compilers, optimization, E.1 [Data, Data Structures|arrays, G.2.2 [Discrete mathematics, Graph Theory|trees General Terms, Algorithms, Languages, Theory

Popis souboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.39.4144

Dostupnost: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.39.4144

GATS 1.0: A Novel GA-based Scheduling Algorithm for Task Scheduling

Autoři: Mohammad Daoud Nawwaf Kharma The Pennsylvania State University CiteSeerX Archives

Přispěvatelé: Mohammad Daoud Nawwaf Kharma The Pennsylvania State University CiteSeerX Archives

Zdroj: http://www.cs.bham.ac.uk/~wbl/biblio/gecco2005/docs/p2209.pdf.

Témata: Categories and Subject Descriptors C.1.2 [Processor Architectures, Multiple Data Stream Architectures (Multiprocessors) – multiple-instruction-stream, multiple-data-stream processors (MIMD, D.1.3 [Programming Techniques, Concurrent Programming – distributed programming, parallel programming, D.4.1 [Operating Systems, Process Management – scheduling, F.1.2 [Computation by Abstract Devices, Modes of Computation – parallelism and concurrency. General Terms Algorithms, Performance, Design. Keywords Genetic algorithm, parallel processing, scheduling, heterogeneous

Popis souboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.420.6257; http://www.cs.bham.ac.uk/~wbl/biblio/gecco2005/docs/p2209.pdf

Dostupnost: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.420.6257
http://www.cs.bham.ac.uk/~wbl/biblio/gecco2005/docs/p2209.pdf

SMP-SoC is the Answer if You Ask the Right Questions

Autoři: Philip Machanick The Pennsylvania State University CiteSeerX Archives

Přispěvatelé: Philip Machanick The Pennsylvania State University CiteSeerX Archives

Zdroj: http://www.itee.uq.edu.au/~philip/Publications/_SAICSIT/SMP-SoC.pdf.

Témata: Categories and Subject Descriptors, C.1.2 [Processor Architectures, C.1.2 Multiple Data Stream Architectures (Multiprocessors)—Multiple-instruction-stream, multiple-data-stream processors (MIMD, C.4 [Processor Performance of Systems, — Design Studies General Terms, Measurement, Performance, Design Additional Key Words and Phrases, chip multiprocessor, system on chip, high performance computing, embedded systems

Popis souboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.304.2641

Dostupnost: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.304.2641
http://www.itee.uq.edu.au/~philip/Publications/_SAICSIT/SMP-SoC.pdf

Asymmetric Memory Fences: Optimizing Both Performance and Implementability ∗

Autoři: Yuelu Duan Nima Honarm Josep Torrellas a další

Přispěvatelé: Yuelu Duan Nima Honarm Josep Torrellas a další

Zdroj: http://iacoma.cs.uiuc.edu/iacoma-papers/asplos15.pdf.

Témata: Categories and Subject Descriptors C.1.2 [Processor Ar- chitectures, Multiple Data Stream Architectures (Multipro- cessors)- Multiple-instruction-stream, multiple-data-stream processors (MIMD, D.1.3 [Programming Techniques, Concurrent Programming- Parallel programming. Keywords Fences, Sequential Consistency, Synchroniza- tion, Parallel Programming, Shared-Memory Machines

Popis souboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.696.7295

Dostupnost: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.696.7295
http://iacoma.cs.uiuc.edu/iacoma-papers/asplos15.pdf

Investigating the Performance of Collective Communications on SMP Clusters: A Case for MPI_Allgather.

Autoři: Gu, Feng Long Nzigou M., Hyacinthe de Melo Baptista Domingues, Guilherme a další

Zdroj: AIP Conference Proceedings; 12/26/2007, Vol. 963 Issue 2, p52-56, 5p, 3 Diagrams, 3 Graphs

Témata: COMPUTERS, PARALLEL computers, COMPUTER architecture, SYSTEMS development, MOLECULAR structure, MAGNETIC susceptibility

Compiling Geometric Paradigms through Local Communications

Autoři: Salvatore Orlando Marco Vanneschi The Pennsylvania State University CiteSeerX Archives

Přispěvatelé: Salvatore Orlando Marco Vanneschi The Pennsylvania State University CiteSeerX Archives

Zdroj: http://www.dsi.unive.it/~orlando/IFIP-geom.ps.Z.

Témata: C.1.2, D.1.3, D.2.2 Keywords, Processor architectures, Multiple Data Stream Architectures (Multiprocessors, Programming techniques, Concurrent Programming, Software Engineering, Tools and Techniques

Popis souboru: application/postscript

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.54.4760

Dostupnost: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.54.4760
http://www.dsi.unive.it/~orlando/IFIP-geom.ps.Z

Cellular array processor CAP and applications.

Autoři: Ishii, Mitsuo Sato, Hiroyuki Ikesaka, Morio a další

Zdroj: Journal of VLSI Signal Processing; Aug1989, Vol. 1 Issue 1, p57-67, 11p

The ETH multiprocessor project: parallel simulation of continuous systems.

Autoři: Halin, Hans J. Bührer, Richard Halg, Walter

Zdroj: Simulation; Oct1980, Vol. 35 Issue 4, p109-123, 15p

Minimizing Communication in the Bitonic Sort.

Autoři: Jae-Dong Lee Batcher, Kenneth E.

Zdroj: IEEE Transactions on Parallel & Distributed Systems; May2000, Vol. 11 Issue 5, p459, 16p, 2 Black and White Photographs, 20 Diagrams, 2 Charts

Témata: SORTING (Electronic computers), PARALLEL computers