Search Results - Multiple Data Stream Architectures—array and vector processors~

Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators

Authors: Yunsup Lee Rimas Avizienis Alex Bishara et al.

Contributors: Yunsup Lee Rimas Avizienis Alex Bishara et al.

Source: http://cseweb.ucsd.edu/~marora/cse290/sp11/papers/batten2011.pdf.

Subject Terms: Categories and Subject Descriptors C.1.2 [Processor Architectures, Multiple Data Stream Architectures—array and vector processors, MIMD, SIMD General Terms

File Description: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.393.744; http://cseweb.ucsd.edu/~marora/cse290/sp11/papers/batten2011.pdf

Availability: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.393.744
http://cseweb.ucsd.edu/~marora/cse290/sp11/papers/batten2011.pdf

Diagnosability of regular systems

Authors: Caruso A. Chessa S. Maestrini P. et al.

Source: ISTI Technical reports, pp.1–18, 2001

Subject Terms: control structures and microprogramming: control structure reliability, Processors architectures: multiple data stream architectures ..Array and vector processors, Operating systems: reliability .. fault. Tolerance, Testing and fault. Tolerance .. Diagnostics, performance and reliability: reliability, testing and fault. Tolerance

Access URL: http://www.cnr.it/prodotto/i/160466
https://publications.cnr.it/doc/160466

Efficient Data Exchange between WebAssembly Modules.

Authors: Silva, Lucas Metrôlho, José Ribeiro, Fernando

Source: Future Internet; Sep2024, Vol. 16 Issue 9, p341, 31p

Subject Terms: PROGRAMMING languages, VIRTUAL machine systems, DATA structures, CODE generators, WEB browsers

ELM-NET, a closer to practice approach for classifying the big data using multiple independent ELMs.

Authors: Shokrzade, Amin Tab, Fardin Akhlaghian Ramezani, Mohsen

Source: Cluster Computing; Jun2020, Vol. 23 Issue 2, p735-757, 23p

Subject Terms: RUNNING training, BIG data, TEST methods

Introduction to the Systems Approach.

Authors: Flynn, Michael J. Luk, Wayne

Source: Computer System Design; 2011, p1-38, 38p

A Survey of Near-Data Processing Architectures for Neural Networks.

Authors: Hassanpour, Mehdi Riera, Marc González, Antonio

Source: Machine Learning & Knowledge Extraction; Mar2022, Vol. 4 Issue 1, p66-102, 37p

Subject Terms: ARTIFICIAL intelligence, MACHINE learning, COMPUTER systems, DEEP learning

Subject Index.

Authors: Zomaya, Albert Y. Sinnen, Oliver

Source: Task Scheduling for Parallel Systems; 2007, p285-296, 12p

DMPRA: A Dynamic Reconfiguration Mechanism for a Dual-Mode Programmable Reconfigurable Array Architecture.

Authors: Li, Kangle Jiang, Lin Huang, Xingjie et al.

Source: Journal of Circuits, Systems & Computers; Jun2023, Vol. 32 Issue 9, p1-27, 27p

Subject Terms: GATE array circuits, VIDEO coding, CLOCKS & watches, MULTICASTING (Computer networks)

A Novel Algorithm for Online Inexact String Matching and its FPGA Implementation.

Authors: Cinti, Alessandro Bianchi, Filippo Maria Martino, Alessio et al.

Source: Cognitive Computation; Mar2020, Vol. 12 Issue 2, p369-387, 19p

Parallel Implementation of the CCSDS 1.2.3 Standard for Hyperspectral Lossless Compression.

Authors: Báscones, Daniel González, Carlos Mozos, Daniel

Source: Remote Sensing; Oct2017, Vol. 9 Issue 10, p973, 17p

Subject Terms: HYPERSPECTRAL imaging systems, REMOTE sensing, ARRAY processors, FIELD programmable gate arrays, AIRBORNE Visible/Infrared Imaging Spectrometer (AVIRIS)

The simultaneous optical multiprocessor exchange bus.

Authors: Kulick, J. Cohen, W.E. Katsinis, C. et al.

Source: Proceedings of Second International Workshop on Massively Parallel Processing Using Optical Interconnections; 1995, p336-344, 9p

Intensive Data Management in Parallel Systems: A Survey.

Authors: Khan, M.F. Paul, Ray Ahmed, Ishfaq et al.

Source: Distributed & Parallel Databases; Oct1999, Vol. 7 Issue 4, p383-414, 32p

A Parallel Algorithm for Volume Projections on SIMD Mesh-Connected Computers.

Authors: Li, Hongzheng Shi, Hongchi

Source: Journal of Supercomputing; Aug2000, Vol. 17 Issue 1, p5-22, 18p

Computing all-pairs shortest paths on a linear systolic array and hardware realization on a reprogrammable FPGA platform.

Authors: Milovanović, E. Milovanović, I. Bekakos, M. et al.

Source: Journal of Supercomputing; Apr2007, Vol. 40 Issue 1, p49-66, 18p, 6 Diagrams, 6 Charts, 3 Graphs

Subject Terms: SYSTOLIC array circuits, DIRECTED graphs, COMPUTER simulation, LINEAR electric circuits, ALGORITHMS, VECTOR processing (Computer science), COMPUTER software, COMPUTER engineering, COMPUTER science

Simulation and Analysis of DIT FFT Algorithm for Spartan 3 FPGA.

Authors: Verma, Manoj Sindal, Ravi

Source: 2013 International Conference on Communication Systems & Network Technologies; 2013, p721-726, 6p

Multicore Compilation Strategies and Challenges.

Authors: Mehrara, Mojtaba Jablin, Thomas Upton, Dan et al.

Source: IEEE Signal Processing Magazine; Nov2009, Vol. 26 Issue 6, p55-63, 9p

Problems of Designing Supersystems with Dynamic Architectures.

Authors: Kartashev

Source: IEEE Transactions on Computers; 1980, Vol. C-29 Issue 12, p1114-1132, 19p

Identity-plus-row matrix decomposition and its application in design of parallel projection algorithms.

Authors: Li, Hongzheng Shi, Hongchi

Source: Journal of Electronic Imaging; Jul2001, Vol. 10 Issue 3, p814-824, 11p

Specification, Evaluation And Selection Of A Host/array System.

Authors: Billerbeck, G.N.

Source: COMPCON '77; 1977, p58-63, 6p

Parallel FFT on ATM based networks of workstations.

Authors: Chalasani, Suresh Ramanathan, Parameswaran

Source: Cluster Computing; May1998, Vol. 1 Issue 1, p13-26, 14p