Search Results - Loop Parallelization Algorithm

Plugging anti and output dependence removal techniques into loop parallelization algorithm

Authors: Calland, Pierre-Yves Darte, Alain Robert, Yves et al.

Contributors: Calland, Pierre-Yves Darte, Alain Robert, Yves et al.

Source: Parallel Computing. 23:251-266

Subject Terms: loop parallelization algorithm, output dependence, [INFO.INFO-DC] Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], 0202 electrical engineering, electronic engineering, information engineering, Distributed algorithms, dependence removal, 02 engineering and technology, anti dependence

File Description: application/xml

Access URL: http://graal.ens-lyon.fr/~fvivien/Publications/Plugging.pdf
https://inria.hal.science/hal-00856884v1
https://doi.org/10.1016/s0167-8191(96)00108-1
https://www.sciencedirect.com/science/article/pii/S0167819196001081
http://graal.ens-lyon.fr/~fvivien/Publications/Plugging.pdf
http://www.sciencedirect.com/science/article/pii/S0167819196001081
http://dblp.uni-trier.de/db/journals/pc/pc23.html#CallandDRV97
https://hal.inria.fr/inria-00073783/document
https://hal.inria.fr/inria-00073783

The Batched DOACROSS loop parallelization algorithm

Authors: Guido Araujo Divino César Soares Lucas

Source: 2015 International Conference on High Performance Computing & Simulation (HPCS). :476-483

Subject Terms: 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, 01 natural sciences, 3. Good health

Access URL: http://ieeexplore.ieee.org/document/7237079/
https://dblp.uni-trier.de/db/conf/ieeehpcs/ieeehpcs2015.html#LucasA15
https://ieeexplore.ieee.org/document/7237079/

Index Dependent Nested Loops Parallelization with an Even Distributed Number of Steps.

Alternate Title: Predstavljena je metoda paralelizma za posebno vrsto vgnezdenih zank.

Authors: Pintér, Ádám Szénási, Sándor

Source: Informatica (03505596). Dec2021, Vol. 45 Issue 4, p493-506. 14p.

Subject Terms: High performance computing, Parallel algorithms, Parallel processing

Loop Parallelization Algorithm for Specific Case of Loop-carried Dependence for Hardware Compilation

Authors: A.A. Uvarov R.Kh. Sadykhov

Source: 2007 4th IEEE Workshop on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications. :265-267

Subject Terms: 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology

Access URL: http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000004488418
https://ieeexplore.ieee.org/document/4488418/
http://ieeexplore.ieee.org/document/4488418/

A loop parallelization algorithm for HPF compilers

Authors: Kazuaki Ishizaki Hideaki Komatsu

Source: Lecture Notes in Computer Science ISBN: 9783540607656

Access URL: https://link.springer.com/chapter/10.1007%2FBFb0014199
https://rd.springer.com/chapter/10.1007%2FBFb0014199
https://dblp.uni-trier.de/db/conf/lcpc/lcpc1995.html#IshizakiK95

Parallelization for Multi-dimensional Loops with Non-uniform Dependences.

Authors: Sam-Jin Jeong¹ sjjeong@bu.ac.kr

Source: IAENG International Journal of Computer Science. Feb2018, Vol. 45 Issue 1, p107-111. 5p.

Subject Terms: Loops (Group theory), Parallelizing compilers, Software engineers, Integers, Parallel algorithms

A New Approach to Parallelization of Serial Nested Loops Using Genetic Algorithms.

Authors: Parsa, Saeed Lotfi, Shahriar

Source: Journal of Supercomputing. Apr2006, Vol. 36 Issue 1, p83-94. 12p. 1 Diagram, 2 Charts, 1 Graph.

Subject Terms: *PARALLEL processing, *GENETIC algorithms, *COMPUTER software, *ELECTRONIC data processing, *SUPERCOMPUTERS, *NUMERICAL analysis software, *MULTIPROCESSORS, *COMPUTERS, *COMPUTER science, *TECHNOLOGY

Time Stamp Algorithms for Runtime Parallelization of DOACROSS Loops with Dynamic Dependences.

Authors: Cheng-Zhong Xu Chaudhary, Vipin

Source: IEEE Transactions on Parallel & Distributed Systems. May2001, Vol. 12 Issue 5, p433. 18p. 2 Black and White Photographs, 6 Charts, 13 Graphs.

Subject Terms: *PARALLEL processing, *ALGORITHMS

Compiler and runtime based parallelization & optimization for GPUs

Authors: Ozen, Guray

Contributors: University/Department: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors

Thesis Advisors: Labarta Mancho, Jesús, Ayguadé i Parra, Eduard

Source: TDX (Tesis Doctorals en Xarxa)

Subject Terms: Àrees temàtiques de la UPC::Informàtica

File Description: application/pdf

Access URL: http://hdl.handle.net/10803/664285
https://dx.doi.org/10.5821/dissertation-2117-125844

Simulaciones numéricas en modelos de loops

Authors: Serna Martínez, Pablo

Thesis Advisors: Somoza Gimeno, Andrés M, Ortuño Ortín, Miguel, Universidad de Murcia. Departamento de Física

Source: TDR (Tesis Doctorales en Red)

Subject Terms: Física estadística-Problemas, ejercicios, Transformaciones de fase (Física estadística), Física

File Description: application/pdf

Access URL: http://hdl.handle.net/10803/146182

Quantifier elimination in automatic loop parallelization

Authors: Größlinger, Armin Griebl, Martin Lengauer, Christian

Source: Journal of Symbolic Computation. Nov2006, Vol. 41 Issue 11, p1206-1221. 16p.

Subject Terms: *ALGORITHMS, *GEOMETRY, *ALGEBRA, *FOUNDATIONS of arithmetic

Towards automatic binary runtime loop de-parallelization using on-stack replacement.

Authors: Yusuf, Marwa El-Mahdy, Ahmed Rohou, Erven

Source: Information Processing Letters. May2019, Vol. 145, p53-57. 5p.

Subject Terms: *ALGORITHMS, *FINITE element method, PARALLEL algorithms, NUMERICAL analysis, SYNCHRONIZATION

Plugging Anti and Output Dependence Removal Techniques into Loop Parallelization Algorithms

Authors: Pierre-yves Calland Alain Darte Yves Robert et al.

Contributors: Pierre-yves Calland Alain Darte Yves Robert et al.

Source: http://icps.u-strasbg.fr/~vivien/Publications/Plugging.ps.gz.

File Description: application/postscript

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.48.9710

Availability: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.48.9710
http://icps.u-strasbg.fr/~vivien/Publications/Plugging.ps.gz

OpenMP Parallelization of Dynamic Programming and Greedy Algorithms

Authors: Tadonki, Claude

Index Terms: Computer Science - Distributed, Parallel, and Cluster Computing, text

URL: http://arxiv.org/abs/2001.07103

Loop pipelining with resource and timing constraints

Authors: Sánchez Carracedo, Fermín

Contributors: University/Department: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors

Thesis Advisors: Cortadella, Jordi (Cortadella Fortuny)

Source: TDX (Tesis Doctorals en Xarxa)

Subject Terms: timing contraints, resource constraints, software pipeling, loop pipelining

File Description: application/pdf

Access URL: http://www.tdx.cat/TDX-0204108-105847
http://hdl.handle.net/10803/5998
https://dx.doi.org/10.5821/dissertation-2117-93313

Parallel algorithms for computational fluid dynamics on unstructured meshes

Authors: Borrell Pol, Ricard

Contributors: University/Department: Universitat Politècnica de Catalunya. Departament de Màquines i Motors Tèrmics

Thesis Advisors: Oliva, Asensio, Rodríguez Pérez, Ivette, Colomer Rey, Guillem

Source: TDX (Tesis Doctorals en Xarxa)

File Description: application/pdf

Access URL: http://hdl.handle.net/10803/124702
https://dx.doi.org/10.5821/dissertation-2117-94977

Unfittted finite element methods for explicit boundary representations

Authors: Martorell Pol, Pere Antoni

Contributors: University/Department: Universitat Politècnica de Catalunya. Escola Tècnica Superior d'Enginyers de Camins, Canals i Ports de Barcelona

Thesis Advisors: Badia, Santiago, Verdugo Rojano, Francesc

Source: TDX (Tesis Doctorals en Xarxa)

Subject Terms: Àrees temàtiques de la UPC::Matemàtiques i estadística

File Description: application/pdf

Access URL: http://hdl.handle.net/10803/690625
https://dx.doi.org/10.5821/dissertation-2117-406723

Logical inference techniques for loop parallelization

Authors: Oancea, Cosmin Eugen Rauchwerger, Lawrence

Source: Oancea , C E & Rauchwerger , L 2012 , Logical inference techniques for loop parallelization . in Proceedings of the 33rd ACM SIGPLAN Conference on Programming Language Design and Implementation . Association for Computing Machinery , pp. 509-520 , 33rd ACM SIGPLAN conference on Programming Language Design and Implementation , Beijing , China , 11/06/2012 .

Index Terms: contributionToPeriodical

URL: https://researchprofiles.ku.dk/da/publications/logical-inference-techniques-for-loop-parallelization(c4adcb05-2d72-4c5b-b20c-3b9949d6a1b6).html
https://doi.org/10.1145/2254064.2254124

Coarse-grained loop parallelization: Iteration Space Slicing vs affine transformations

Authors: Beletska, Anna Bielecki, Wlodzimierz Cohen, Albert et al.

Source: Parallel Computing. Aug2011, Vol. 37 Issue 8, p479-497. 19p.

Subject Terms: *PARALLEL computers, *ITERATIVE methods (Mathematics), *AFFINE geometry, *ALGORITHMS, *COMPUTER programming, *INFORMATION storage & retrieval systems

Loop parallelization: revisiting framework of unimodular transformations

Authors: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions Torres Viñals, Jordi et al.

Index Terms: Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, Parallel algorithms, Parallel programming (Computer science), Graph theory, Optimising compilers, Algorismes paral·lels, Programació en paral·lel (Informàtica), Grafs, Teoria de, Conference report

URL: http://hdl.handle.net/2117/112468
http://ieeexplore.ieee.org/document/500615/
http://ieeexplore.ieee.org/document/500615