Suchergebnisse - Loop Level Parallelization

Loop Level Parallelization of a Seismic Inversion Code

Autoren: Symes, William W. Kern, Michel

Weitere Verfasser: Symes, William W. Kern, Michel

Quelle: SEG Technical Program Expanded Abstracts 1993. :189-192

Schlagwörter: parallel computing, autotasking, [INFO.INFO-DC] Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], 0202 electrical engineering, electronic engineering, information engineering, Seismic inversion, [SDU.STU.GP] Sciences of the Universe [physics]/Earth Sciences/Geophysics [physics.geo-ph], 02 engineering and technology, [MATH.MATH-NA] Mathematics [math]/Numerical Analysis [math.NA], 01 natural sciences, 0105 earth and related environmental sciences

Dateibeschreibung: 12 pp; application/pdf

Zugangs-URL: https://scholarship.rice.edu/bitstream/1911/101789/1/TR93-06.pdf
https://inria.hal.science/hal-01315571v1
https://doi.org/10.1190/1.1822434
https://hal.inria.fr/hal-01315571
https://onepetro.org/SEGAM/proceedings-pdf/SEG93/All-SEG93/SEG-1993-0189/1979831/seg-1993-0189.pdf
https://core.ac.uk/display/23478182
https://scholarship.rice.edu/handle/1911/101789

Compiler and runtime based parallelization & optimization for GPUs

Autoren: Ozen, Guray

Weitere Verfasser: University/Department: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors

Thesis Advisors: Labarta Mancho, Jesús, Ayguadé i Parra, Eduard

Quelle: TDX (Tesis Doctorals en Xarxa)

Schlagwörter: Àrees temàtiques de la UPC::Informàtica

Dateibeschreibung: application/pdf

Zugangs-URL: http://hdl.handle.net/10803/664285
https://dx.doi.org/10.5821/dissertation-2117-125844

Just-in-Time Compilation-Inspired Methodology for Parallelization of Compute Intensive Java Code

Autoren: Ghulam Mustafa Waqar Mahmood Muhammad Usman Ghani

Quelle: Mehran University Research Journal of Engineering and Technology, Vol 36, Iss 1, Pp 67-88 (2017)

Schlagwörter: FOS: Computer and information sciences, Parallel computing, Exploit, Technology, Execution time, Computer Networks and Communications, Science, Compiler, Dynamic compilation, 02 engineering and technology, Cloud Computing and Big Data Technologies, Speedup, Multicore Architectures, Parallel Computing, Distributed Grid Computing Systems, Automatic parallelization, Computer security, Just-in-Time Compilation, Parallel Computing and Performance Optimization, 0202 electrical engineering, electronic engineering, information engineering, Multi-core processor, Performance Optimization, Geology, Hotspot (geology), FOS: Earth and related environmental sciences, Multicore System, Engineering (General). Civil engineering (General), Computer science, Task Scheduling, Programming language, High-Performance Computing, Geophysics, Hardware and Architecture, Computer Science, Physical Sciences, TA1-2040, Runtime Analysis, Loop Level Parallelization, Java Virtual Machine, Java, Information Systems

Zugangs-URL: http://publications.muet.edu.pk/index.php/muetrj/article/download/342/156
https://doaj.org/article/2b540e168ad44efcbeec7a6bec73c467
https://core.ac.uk/display/90902586
https://doaj.org/article/2b540e168ad44efcbeec7a6bec73c467
http://ui.adsabs.harvard.edu/abs/2017MURJE..36...67M/abstract

High-level compiler analysis for OpenMP

Autoren: Royuela Alcázar, Sara

Weitere Verfasser: University/Department: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors

Thesis Advisors: Martorell, Xavier (Martorell Bofill)

Quelle: TDX (Tesis Doctorals en Xarxa)

Schlagwörter: Compiler analysis, OpenMP, Task dependency graph, Correctness, Safety-critical, Àrees temàtiques de la UPC::Informàtica

Dateibeschreibung: application/pdf

Zugangs-URL: http://hdl.handle.net/10803/620642
https://dx.doi.org/10.5821/dissertation-2117-121011

Loop Level Parallelization of a Seismic Inversion Code

Autoren: M. Kern W. W. Symes The Pennsylvania State University CiteSeerX Archives

Weitere Verfasser: M. Kern W. W. Symes The Pennsylvania State University CiteSeerX Archives

Quelle: ftp://ftp.caam.rice.edu/pub/people/trip/abstract/kern/kern1.ps.gz

Dateibeschreibung: application/postscript

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.38.949

Verfügbarkeit: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.38.949

R/parallel Parallel Computing for R in non‐dedicated environments

Autoren: Vera Rodríguez, Gonzalo

Weitere Verfasser: University/Department: Universitat Autònoma de Barcelona. Departament d'Arquitectura de Computadors i Sistemes Operatius

Thesis Advisors: Suppi Boldrito, Remo

Quelle: TDX (Tesis Doctorals en Xarxa)

Schlagwörter: Parallel loops, Oportunistic computing, Bioinformatics, Tecnologies

Dateibeschreibung: application/pdf

Zugangs-URL: http://hdl.handle.net/10803/121248

Thread-level parallelization and optimization of NWChem for the Intel MIC architecture

Autoren: Shan, Hongzhang Williams, Samuel de Jong, Wibe et al.

Quelle: Proceedings of the 6th International Workshop on Programming Models and Applications for Multicores and Manycores Pmam 2015

Schlagwörter: 33 Built Environment and Design (for-2020), 40 Engineering (for-2020), 4008 Electrical Engineering (for-2020), 3301 Architecture (for-2020)

Dateibeschreibung: application/pdf

Zugangs-URL: https://escholarship.org/uc/item/4q583014
https://escholarship.org/content/qt4q583014/qt4q583014.pdf

Loop pipelining with resource and timing constraints

Autoren: Sánchez Carracedo, Fermín

Weitere Verfasser: University/Department: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors

Thesis Advisors: Cortadella, Jordi (Cortadella Fortuny)

Quelle: TDX (Tesis Doctorals en Xarxa)

Schlagwörter: timing contraints, resource constraints, software pipeling, loop pipelining

Dateibeschreibung: application/pdf

Zugangs-URL: http://www.tdx.cat/TDX-0204108-105847
http://hdl.handle.net/10803/5998
https://dx.doi.org/10.5821/dissertation-2117-93313

Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework.

Autoren: Qiang Liu Constantinides, George A. Masselos, Konstantinos et al.

Quelle: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Mar2009, Vol. 28 Issue 3, p305-315, 11p

Schlagwörter: OPTIMAL designs (Statistics), INTEGRATED circuit design, VERY large scale circuit integration, COMPUTER simulation of integrated circuits, FIELD programmable gate arrays, PROGRAMMABLE logic devices, GATE array circuits

Unfittted finite element methods for explicit boundary representations

Autoren: Martorell Pol, Pere Antoni

Weitere Verfasser: University/Department: Universitat Politècnica de Catalunya. Escola Tècnica Superior d'Enginyers de Camins, Canals i Ports de Barcelona

Thesis Advisors: Badia, Santiago, Verdugo Rojano, Francesc

Quelle: TDX (Tesis Doctorals en Xarxa)

Schlagwörter: Àrees temàtiques de la UPC::Matemàtiques i estadística

Dateibeschreibung: application/pdf

Zugangs-URL: http://hdl.handle.net/10803/690625
https://dx.doi.org/10.5821/dissertation-2117-406723

Digital design and experimental validation of high-performance real-time OFDM systems

Autoren: Font Bach, Josep Oriol

Weitere Verfasser: University/Department: Universitat Politècnica de Catalunya. Departament de Teoria del Senyal i Comunicacions

Thesis Advisors: Pascual Iserte, Antonio, Bartzoudis, Nikolaos

Quelle: TDX (Tesis Doctorals en Xarxa)

Time: 621.3

Dateibeschreibung: application/pdf

Zugangs-URL: http://hdl.handle.net/10803/129095
https://dx.doi.org/10.5821/dissertation-2117-95071

Pushing Loop-Level Parallelization to the Limit

Autoren: an Mey, Dieter Haarmann, Thomas Koschel, Wolfgang

Quelle: Proceedings of the 4th European Workshop on OpenMP (EWOMP'02), Rom, Italien, , September 2002 ; Proceedings of the 4th European Workshop on OpenMP (EWOMP'02), Rom, Italien, , September 2002 4. European Workshop on OpenMP, EWOMP'02, Rom, Italy, 2002-09

Schlagwörter: info:eu-repo/classification/ddc/004, Informatik

Geographisches Schlagwort: DE

Verfügbarkeit: https://publications.rwth-aachen.de/record/200901
https://publications.rwth-aachen.de/search?p=id:%22RWTH-CONV-200379%22

Efficient hardware/software co-designed schemes for low-power processors

Autoren: López Muñoz, Pedro

Weitere Verfasser: University/Department: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors

Thesis Advisors: Latorre Salinas, Fernando, Gibert Codina, Enric

Quelle: TDX (Tesis Doctorals en Xarxa)

Dateibeschreibung: application/pdf

Zugangs-URL: http://hdl.handle.net/10803/144619
https://dx.doi.org/10.5821/dissertation-2117-95292

Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework

Autoren: Liu, Q Constantinides, GA Masselos, K et al.

Quelle: 2008 International Conference on Field Programmable Logic and Applications. :179-184

Schlagwörter: 0209 industrial biotechnology, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology

Zugangs-URL: http://users.uop.gr/%7Ekmas/J28%20IEEE%20TCAD%20data%20reuse%20parallelism%20combo%202009.pdf
http://hdl.handle.net/10044/1/15302

Programming models to support data science workflows

Autoren: Ramón-Cortés Vilarrodona, Cristián

Weitere Verfasser: University/Department: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors

Thesis Advisors: Badia Sala, Rosa M. (Rosa Maria), Ejarque Artigas, Jorge

Quelle: TDX (Tesis Doctorals en Xarxa)

Schlagwörter: Distributed computing, High-performance computing, Data science pipelines, Task-ba workflows, Dataflows, Containers (Computer sicience), COMPSs, PyCOMPSs, AutoParallel, Docker, Àrees temàtiques de la UPC::Informàtica

Dateibeschreibung: application/pdf

Zugangs-URL: http://hdl.handle.net/10803/669728
https://dx.doi.org/10.5821/dissertation-2117-330142

Characterization and modelling of micro and nanofluidic systems

Autoren: Licon Bernal, Edxon Eduardo

Weitere Verfasser: University/Department: Universitat Politècnica de Catalunya. Departament d'Enginyeria Química

Thesis Advisors: Yaroshchuk, Andriy

Quelle: TDX (Tesis Doctorals en Xarxa)

Dateibeschreibung: application/pdf

Zugangs-URL: http://hdl.handle.net/10803/288227
https://dx.doi.org/10.5821/dissertation-2117-95665

Combining data reuse exploitation with data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework

Autoren: Qiang Liu George A. Constantinides Konstantinos Masselos et al.

Weitere Verfasser: Qiang Liu George A. Constantinides Konstantinos Masselos et al.

Quelle: http://cas.ee.ic.ac.uk/people/gac1/pubs/QiangFPL08.pdf.

Dateibeschreibung: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.385.9818; http://cas.ee.ic.ac.uk/people/gac1/pubs/QiangFPL08.pdf

Verfügbarkeit: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.385.9818
http://cas.ee.ic.ac.uk/people/gac1/pubs/QiangFPL08.pdf

Parallelizing more loops with compiler guided refactoring

Autoren: Larsen, P Ladelsky, R. Lidman, Jacob et al.

Quelle: Proceedings of the International Conference on Parallel Processing. :410-419

Schlagwörter: Automatic Loop Parallelization, Compiler Feedback, Refactoring

Zugangs-URL: https://research.chalmers.se/publication/169410

SPMD OpenMP versus MPI on a IBM SMP for 3 Kernels of the NAS Benchmarks.

Autoren: Krawezik, Géraud Alléon, Guillaume Cappello, Franck

Quelle: High Performance Computing (9783540436744); 2006, p425-436, 12p

Learning to Parallelize with OpenMP by Augmented Heterogeneous AST Representation

Autoren: Chen, Le Mahmud, Quazi Ishtiaque Phan, Hung et al.

Index Begriffe: Computer Science - Machine Learning, Computer Science - Software Engineering, text

URL: http://arxiv.org/abs/2305.05779