Suchergebnisse - FPGA MATLAB HDL CODER VHDL Hardware Security

A Comparative Study between MATLAB HDL Coder and VHDL for FPGAs Design and implementation

Autoren: Elsayed, Ghada Kayed, Somaya

Quelle: Journal of International Society for Science and Engineering. 0:0-0

Schlagwörter: FPGA MATLAB HDL CODER VHDL Hardware Security, Computer Engineering, Electrical and Computer Engineering

Chaotic or Hyper-chaotic Oscillator? Numerical Solution, Circuit Design, MATLAB HDL-Coder Implementation, VHDL Code, Security Analysis, and FPGA Realization

Autoren: Talal Bonny

Quelle: Circuits, Systems, and Signal Processing. 40:1061-1088

Schlagwörter: 0103 physical sciences, 01 natural sciences

Zugangs-URL: https://dblp.uni-trier.de/db/journals/cssp/cssp40.html#Bonny21
https://link.springer.com/article/10.1007/s00034-020-01521-8

FPGA Design and Implementation for Montgomery Multiplication Algorithm Using MATLAB HDL Coder

Autoren: Ghada Elsayed Eman S. Abass

Quelle: Bulletin of the National Research Centre, Vol 48, Iss 1, Pp 1-16 (2024)

Schlagwörter: Science, MATLAB HDL coder, 02 engineering and technology, Electrical and Computer Engineering, Cryptographic co-processors, HDL coder, Security, 0202 electrical engineering, electronic engineering, information engineering, Computer Engineering, FPGA, Matlab

Zugangs-URL: https://doaj.org/article/ba613135c2c14de8b39ee6185e996199

FPGA design and implementation for montgomery multiplication algorithm using MATLAB HDL coder.

Autoren: Elsayed, Ghada Abass, Eman S.

Quelle: Bulletin of the National Research Centre. 12/23/2024, Vol. 48 Issue 1, p1-16. 16p.

Schlagwörter: *VERILOG (Computer hardware description language), *RSA algorithm, *ELLIPTIC curves, *COPROCESSORS, *MULTIPLICATION

FPGA design and implementation for adaptive digital chaotic key generator.

Autoren: Elsayed, Ghada Soleit, Elsayed Kayed, Somaya

Quelle: Bulletin of the National Research Centre; 8/11/2023, Vol. 47 Issue 1, p1-9, 9p

Schlagwörter: DIGITAL technology, COMPUTER software security, DIGITAL signatures, RANDOM numbers, INFORMATION technology security, IMAGE encryption

Hardware Acceleration of Video Edge Detection with Hight Level Synthesis on the Xilinx Zynq Platform.

Autoren: Saidani, Taoufik Ghodhbani, Refka

Quelle: Engineering, Technology & Applied Science Research; Feb2022, Vol. 12 Issue 1, p8007-8012, 6p

Schlagwörter: RAPID prototyping, VIDEO processing, EDGES (Geometry), VIDEOS, HARDWARE

Chaotic or Hyper-chaotic Oscillator? Numerical Solution, Circuit Design, MATLAB HDL-Coder Implementation, VHDL Code, Security Analysis, and FPGA Realization.

Autoren: Bonny, Talal

Quelle: Circuits, Systems & Signal Processing; Mar2021, Vol. 40 Issue 3, p1061-1088, 28p

Schlagwörter: GATE array circuits, CHAOTIC communication, NONLINEAR oscillators, ELECTRIC oscillators

Performance Evaluation of FPGA-Based Design of Modified Chua Oscillator.

Autoren: Taşdemir, Muhammed Furkan Litvinenko, Anna Koyuncu, İsmail et al.

Quelle: Chaos Theory & Applications (CHTA); 2024, Vol. 6 Issue 4, p249-256, 8p

Schlagwörter: NUMBER systems, POPULARITY, ALGORITHMS

Real Time FPGA Implementation of an Efficient High Speed Harris Corner Detection Algorithm Based on High-Level Synthesis.

Autoren: Ghodhbani, Refka Saidani, Taoufik Alhomoud, Ahmed et al.

Quelle: Engineering, Technology & Applied Science Research; Dec2023, Vol. 13 Issue 6, p12169-12174, 6p

Schlagwörter: ARCHITECTURAL design, COMPUTER vision, ALGORITHMS, STREAMING video & television, IMAGE processing, MICROPROCESSORS

Rapid Prototyping for Design and Test of FPGA-Based Model Predictive Controllers for Power Converters.

Autoren: Purraji, Marziye Zamiri, Elyas Sanchez, Alberto et al.

Quelle: Journal of Electrical Engineering & Technology (19750102); May2025, Vol. 20 Issue 4, p2419-2438, 20p

Progressive Cyclical Convolutional Neural Network for embedded vision based Internet of Things using VLSI.

Autoren: Jayakumar, S. Gouthami, Koduru Chanthirasekaran, K. et al.

Quelle: Analog Integrated Circuits & Signal Processing; Dec2025, Vol. 125 Issue 3, p1-12, 12p

Efficient Hardware-in-the-Loop Models Using Automatic Code Generation with MATLAB/Simulink.

Autoren: Saralegui, Roberto Sanchez, Alberto de Castro, Angel

Quelle: Electronics (2079-9292); Jul2023, Vol. 12 Issue 13, p2786, 18p

Schlagwörter: GATE array circuits, AUTOMATIC control systems, RUNGE-Kutta formulas, WORKFLOW management

A Reconfigurable Hardware Realization for Real-Time Simulation of Cardiac Excitation and Conduction.

Autoren: Mahmud, Farhanahani Adon, Nur Atiqah Othman, Norliza et al.

Quelle: International Journal of Integrated Engineering (IJIE); 2024, Vol. 16 Issue 1, p272-281, 10p

Real Time FPGA Implementation of a High Speed for Video Encryption and Decryption System with High Level Synthesis Tools.

Autoren: Alhomoud, Ahmed

Quelle: International Journal of Advanced Computer Science & Applications; Jan2024, Vol. 15 Issue 1, p724-731, 8p

Contextual Real-Time Optimization on FPGA by Dynamic Selection of Chaotic Maps and Adaptive Metaheuristics.

Autoren: Ouchker, Rabab Tahiri, Hamza Mchichou, Ismail et al.

Quelle: Applied Sciences (2076-3417); Oct2025, Vol. 15 Issue 19, p10695, 35p

Schlagwörter: FIELD programmable gate arrays, METAHEURISTIC algorithms, MATHEMATICAL optimization, PROBLEM solving, DYNAMIC programming, ARTIFICIAL intelligence

EFFICIENT IMPLEMENTATION OF FRACTIONAL SAMPLING RATE CONVERSION (SRC) ON FPGA.

Autoren: GADAWE, Noor Talal HAMAD, Rasha Waleed QADDOORI, Sahar Lazim

Quelle: Diagnostyka; 2025, Vol. 26 Issue 3, p1-9, 9p

Schlagwörter: DIGITAL signal processing, FIELD programmable gate arrays, DISCRETE time filters, RESOURCE management, ELECTRIC filters, INTERPOLATION

Frequency-Modulated Antipodal Chaos Shift Keying Chaotic Communication on Field Program Gate Array: Prototype Design and Performance Insights.

Autoren: Capligns, Filips Babajans, Ruslans Cirjulina, Darja et al.

Quelle: Applied Sciences (2076-3417); Feb2025, Vol. 15 Issue 3, p1156, 21p

Schlagwörter: TELECOMMUNICATION systems, SIGNAL processing, THERMAL instability, GATE array circuits, CHAOS synchronization, CHAOTIC communication

AHA: Design and Evaluation of Compute-Intensive Hardware Accelerators for AMD-Xilinx Zynq SoCs Using HLS IP Flow.

Autoren: Berrazueta-Mena, David Navas, Byron

Quelle: Computers (2073-431X); May2025, Vol. 14 Issue 5, p189, 35p

Schlagwörter: ARTIFICIAL neural networks, HIGH performance computing, ENCRYPTION protocols, MATRIX multiplications, RAPID prototyping

Enhancing the Dorsal Side of Fingers Using An Image Enhancement Technique with FPGA Output Comparison.

Alternate Title: تحسين الجانب الظهري للأصابع باستخدام تقنية تحسين الصورة من خلال مقارنة مخرجات FPGA. (Arabic)

Autoren: Tan Shu Han Riaz, Imran Ali, Ahmad Nazri

Quelle: Baghdad Science Journal; 2024 Special Issue, Vol. 21, p1840-1849, 10p

Schlagwörter: IMAGE intensifiers, PERSONAL computers, HISTOGRAMS, ALGORITHMS

Design and Implementation of a Real-Time Image Processing System Based on Sobel Edge Detection using Model-based Design Methods.

Autoren: Saidani, Taoufik Ghodhbani, Refka Ben Ammar, Mohamed et al.

Quelle: International Journal of Advanced Computer Science & Applications; 2024, Vol. 15 Issue 3, p273-278, 6p