Search Results - Computation/Dataflow Optimization

Ising-CIM: A Reconfigurable and Scalable Compute Within Memory Analog Ising Accelerator for Solving Combinatorial Optimization Problems.

Authors: Xie, Shanshan Raman, Siddhartha Raman Sundara Ni, Can et al.

Source: IEEE Journal of Solid-State Circuits; Nov2022, Vol. 57 Issue 11, p3453-3465, 13p

Subject Terms: COMBINATORIAL optimization, COMPUTER arithmetic, DIGITAL electronics, ANALOG circuits, ISING model, COMPLEMENTARY metal oxide semiconductors, SPIN valves

OMNI: A Framework for Integrating Hardware and Software Optimizations for Sparse CNNs.

Authors: Liang, Yun Lu, Liqiang Xie, Jiaming

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Aug2021, Vol. 40 Issue 8, p1648-1661, 14p

Subject Terms: APPLICATION-specific integrated circuits, DEEP learning, CONVOLUTIONAL neural networks, INTEGRATED software, GATE array circuits, IMAGE recognition (Computer vision)

Company/Entity: REPUBLICAN Party (U.S. : 1854- ), NATIONAL Academy of Sciences (U.S.)

Intel Corporation

Authors: Kumar N. Lalgudi Marios C. Papaefthymiou The Pennsylvania State University CiteSeerX Archives

Contributors: Kumar N. Lalgudi Marios C. Papaefthymiou The Pennsylvania State University CiteSeerX Archives

Source: http://www.cs.ucla.edu/%7Emiodrag/papers/Lalgudi_July2000.pdf.

Subject Terms: Analysis of Algorithms and Problem Complexity General Terms, Algorithms, Design, Performance Additional Key Words and Phrases, Combinatorial optimization, computation dataflow graphs, embedded systems, high-level synthesis, integer linear programming, retiming, scheduling, vectorization

File Description: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.228.7478; http://www.cs.ucla.edu/%7Emiodrag/papers/Lalgudi_July2000.pdf

Availability: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.228.7478
http://www.cs.ucla.edu/%7Emiodrag/papers/Lalgudi_July2000.pdf

Auto-accel: a SW/HW co-design framework with adaptive unified buffer mapping and power-of-two quantization for FPGA-based object detection accelerators.

Authors: Ko, Junha Lee, Dongjun Kim, Youngchan et al.

Source: Journal of Real-Time Image Processing; Jan2026, Vol. 23 Issue 1, p1-15, 15p

PANDA: Adaptive Prefetching and Decentralized Scheduling for Dataflow Architectures.

Authors: QIN, SHANTIAN FAN, ZHIHUA LI, WENMING et al.

Source: ACM Transactions on Architecture & Code Optimization; Jun2025, Vol. 22 Issue 2, p1-27, 27p

Artificial Intelligence for Business Optimization : Research and Applications

Authors: Bhuvan Unhelkar Tad Gonsalves

Resource Type: eBook.

Subjects: Information technology--Management, Organizational change, Machine learning, Strategic planning, Artificial intelligence--Economic aspects

Categories: COMPUTERS / Artificial Intelligence / General, BUSINESS & ECONOMICS / Development / Business Development, BUSINESS & ECONOMICS / Management Science, BUSINESS & ECONOMICS / Information Management, BUSINESS & ECONOMICS / Office Automation, BUSINESS & ECONOMICS / Organizational Development, COMPUTERS / Business & Productivity Software / Business Intelligence, COMPUTERS / Information Technology, COMPUTERS / Machine Theory, COMPUTERS / Networking / General, COMPUTERS / Software Development & Engineering / Systems Analysis & Design, TECHNOLOGY & ENGINEERING / Automation

A Fully Integrated 1.7mW Attention-Based Automatic Speech Recognition Processor.

Authors: Liou, Yi-Long Hsu, Jui-Yang Chen, Chen-Sheng et al.

Source: IEEE Transactions on Circuits & Systems. Part II: Express Briefs; Oct2022, Vol. 69 Issue 10, p4178-4182, 5p

An Efficient Convolutional Neural Network Accelerator Design on FPGA Using the Layer-to-Layer Unified Input Winograd Architecture.

Authors: Li, Jie Liang, Yong Yang, Zhenhao et al.

Source: Electronics (2079-9292); Mar2025, Vol. 14 Issue 6, p1182, 20p

Subject Terms: CONVOLUTIONAL neural networks, COMPUTER vision, ARTIFICIAL intelligence, GATE array circuits, VISUAL fields

DSA-CNN: an fpga-integrated deformable systolic array for convolutional neural network acceleration.

Authors: Wan, Yi Chen, Junfan Yang, Xiong et al.

Source: Applied Intelligence; Jan2025, Vol. 55 Issue 1, p1-18, 18p

Automatic Deployment of Convolutional Neural Networks on FPGA for Spaceborne Remote Sensing Application.

Authors: Yan, Tianwei Zhang, Ning Li, Jie et al.

Source: Remote Sensing; Jul2022, Vol. 14 Issue 13, p3130-N.PAG, 30p

Subject Terms: CONVOLUTIONAL neural networks, REMOTE sensing, GATE array circuits, IMAGE processing, POWER resources

Efficient Block Scheduling to Minimize Context Switching Time for Programmable Embedded Processors.

Authors: Hong, Inki Potkonjak, Miodrag Papaefthymiou, Marios

Source: Design Automation for Embedded Systems; Oct1999, Vol. 4 Issue 4, p311-327, 17p

Mentor: A Memory-Efficient Sparse-dense Matrix Multiplication Accelerator Based on Column-Wise Product.

Authors: Lu, Xiaobo Fang, Jianbin Peng, Lin et al.

Source: ACM Transactions on Architecture & Code Optimization; Dec2024, Vol. 21 Issue 4, p1-25, 25p

Survey on Redundancy Based-Fault tolerance methods for Processors and Hardware accelerators - Trends in Quantum Computing, Heterogeneous Systems and Reliability.

Authors: Venkatesha, Shashikiran Parthasarathi, Ranjani

Source: ACM Computing Surveys; Nov2024, Vol. 56 Issue 11, p1-76, 76p

Subject Terms: GRAPHICS processing units, REDUCED instruction set computers, ARTIFICIAL intelligence, SOFT errors, ARTIFICIAL neural networks, INSTRUCTION set architecture

A SYSTEM AND METHOD FOR THE UNIFICATION AND OPTIMIZATION OF MACHINE LEARNING INFERENCE PIPELINES

High-Precision Performance Estimation of Dynamic Dataflow Programs.

Authors: Michalska, Malgorzata Casale-Brunet, Simone Bezati, Endri et al.

Source: 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC); 2016, p101-108, 8p

SAC: An Ultra-Efficient Spin-based Architecture for Compressed DNNs.

Authors: YUNPING ZHAO SHENG MA HENG LIU et al.

Source: ACM Transactions on Architecture & Code Optimization; Mar2024, Vol. 21 Issue 1, p1-26, 26p

Machine Learning Hardware Design for Efficiency, Flexibility, and Scalability [Feature].

Authors: Zhang, Jie-Fang Zhang, Zhengya

Source: IEEE Circuits & Systems Magazine; Q3 2023, Vol. 23 Issue 3, p35-53, 19p

Low-Power FPGA Realization of Lightweight Active Noise Cancellation with CNN Noise Classification.

Authors: Park, Seunghyun Park, Daejin

Source: Electronics (2079-9292); Jun2023, Vol. 12 Issue 11, p2511, 16p

Subject Terms: CONVOLUTIONAL neural networks, DIGITAL signal processing, FAST Fourier transforms, NOISE, SIGNAL-to-noise ratio, CLASSIFICATION algorithms, HEADPHONES

TCX: A RISC Style Tensor Computing Extension and a Programmable Tensor Processor.

Authors: TAILIN LIANG LEI WANG SHAOBO SHI et al.

Source: ACM Transactions on Embedded Computing Systems; May2023, Vol. 22 Issue 3, p1-27, 27p

Subject Terms: DEEP learning, REDUCED instruction set computers, MACHINE learning, SOFTWARE compatibility, CONVOLUTIONAL neural networks, SOFTWARE architecture

Company/Entity: TAIWAN Semiconductor Manufacturing Co. Ltd.

Dynamic Sparse Attention for Scalable Transformer Acceleration.

Authors: Liu, Liu Qu, Zheng Chen, Zhaodong et al.

Source: IEEE Transactions on Computers; Dec2022, Vol. 71 Issue 12, p3165-3178, 14p

Subject Terms: COMPUTER vision, MACHINE learning, SPARSE matrices