Search Results - ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.9: Retargetable computers

Retargetable compilers and architecture exploration for embedded processors.

Authors: Leupers, R. Hohenauer, M. Ceng, J. et al.

Source: IEE Proceedings -- Computers & Digital Techniques; Mar2005, Vol. 152 Issue 2, p209-223, 15p

Subject Terms: COMPUTERS, COMPILERS (Computer programs), COMPUTER software, SYSTEMS software, EMBEDDED computer systems, SYSTEMS on a chip, INFORMATION technology

Retargetable Pipeline Hazard Detection for Partially Bypassed Processors.

Authors: Shrivastava, Aviral Earlie, Eugene Dutt, Nikil D. et al.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Aug2006, Vol. 14 Issue 8, p791-801, 11p

Subject Terms: PIPELINES, HYDRAULIC structures, ARCHITECTURAL design, EMBEDDED computer systems, COMPUTERS

支援指令結構描述語言與GCC的結合技術 ; Integrating ADL-family Languages into Machine Descriptions of GCC for Reconfigurable Processors

Authors: 林立峯 Li-Feng Lin 李政崑 et al.

Contributors: 林立峯 Li-Feng Lin 李政崑 et al.

Subject Terms: 嵌入式系統, Design space exploration, 架構描述語言, 可移植性編譯器, GCC, Embedded systems, Architecture description languages, Retargetable compiler

Time: 2

File Description: 155 bytes; text/html

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"A Methodology and Tool Suite for C Compiler generation from ADL Processor Models," Proc. of 7th Design, Automation and Test in Europe (DATE'04), March 2004. [7] Oliver Schliebusch, A. Chattopadhyay, R. Leupers, G. Ascheid, H. Meyr, Mario Steinert, Gunnar Braun, Achim Nohl, "RTL Processor Synthesis for Architecture Exploration and Implementation," Proc. of 7th Design, Automation and Test in Europe (DATE'04), March 2004. [8] A. Ho®mann, H. Meyr, R. Leupers, "Architecture Exploration for Embedded Processors with LISA," Kluwer Academic Publishers, ISBN 1-4020-7338-0, December 2002. [9] Associated Compiler Experts vb: http://www.ace.nl [10] CoWare Inc.: LISATek product family, http://www.coware.com [11] S.Pees, A. Ho®mann, V. ^Zivojnovi¶c, and H. Meyr, "LISA: Machine Description Language for Cycleaccurate Models of Programmable DSP Architectures," Proc. of 35th DAC, 1999. [12] V. ^Zivojnovi¶c, S. Pees, and H. Meyr, "LISA: Machine Description Language and Generic Machine Model for HW/SW Co-design," Proc. of Workshop on VLSI Signal Processing, 1996. [13] C. Siska, "A Processor Description Language Supporting Retargetable Multi-pipeline DSP Program Development Tools," Proc. of 11th ISSS, 1998. [14] Armita Peymandoust, Giovanni De Micheli, "Aymboli Algebra and TimingDriven Data-°ow Synthesis," Proc. of the International Conference on Computer Aided Design 2001 (ICCAD), November 2001. [15] Hiroyuki Tomiyama, Ashok Halambi, Peter Grun, "Architecture Description Languages for Systems-on-Chip Design," Proc. of the Sixth Asia Paci¯c Conference on Chip Design Language, October 1999. [16] J.Sato, A. Y. Alomary, Y. Honma, T. Nakata, A. Shiomi, N. Hikichi, and M. Imai, "PEAS-I: A Hardware/Software Codesign System for ASIP development," IEICE Trans. Fundamentals, E77-A(3):483-491, March 1994. [17] T. Morimoto, K. Yamazaki, H. Nakamura, T. Boku, and K. Nakazawa, "Superscalar Processor Design using Hardware Description Language AIDL," Proc. of APCHDL, 1994. [18] T. Morimoto, K. Saito, H. Nakamura, T. Boku and K.Nakazawa, "Advanced Procssor Design Using Hardware Description Language AIDL," Proc. of ASPDAC, 1997. [19] S. Bashford, U. Bieker, B. harking, R. Leupers, P. Marwedel, A. Neumann, and D. Voggenauer, "The MIMOLA Language Version 4.1," University of Dortmund, 1994. [20] R. Leupers and P. Marwedel, "Retargetable Code Generation Based on Structural Processor Descriptions," Design Automation for Embedded Systems, Kluwer Academic Publishers, 3(1):1-36, January 1998. [21] R. Leupers, "Regargetable Code Generation for Digital Signal Processsors," Kluwer Academic Publishers, 1997. [22] H. Akaboshi, "A Study on Design Support for Computer Architecture Design," PhD Thesis, Dept. of Information Systems, Kyushu University, January 1996. [23] UDL/I Committee, "UDL/I Language Reference Manual Version 2.1.0a," 1994. [24] ASTEM RI. "UDL/I Logic Synthesis System User's Guide Ver. 1.1.0," 1995. [25] M. Freericks, "The nML Machine Description Formalism," Technical Report 1991/15, Fachbereich Informatik, TU Berlin, 1991. [26] F.Lohr, A. Fauth, and M. Freericks, "SIGH/SIM: An Environment for Retargetable Instruction Set Simulation," Technical Report 1993/43, Fachbereich Infomatic, TU Berlin, 1993. [27] D. Lanneer, J. Van Praet, A. Ki°i, K. Schoofs, W. Geurts, F. Thoen, and G. Goossens, "CHESS: Retargetable Code Generation for Embedded DSP Processors," Code Generation for Embedded Processors, Kluwer Acedemic Publishers, 1995. [28] A. Fauth and A. Knoll, \Automatic Generation of DSP Program Development Tools," Proc. of ICASSP, 1993. [29] G. Hadjiyiannis, P, Russo, and S. Devadas, "ISDL: An Instruction Set Description Language for Retargetability," Proc. of 34th DAC, 1997. [30] S. Hanono and S. Devadas, "Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator," Proc. of 35th DAC, 1998. [31] G. Hadjiyiannis, P. Russo, and S. Devadas, "A Methodology for Accurate Performance Evaluation in Architecture Exploration," Proc. of 36th DAC, 1999. [32] J. C. Gyllenhaal, "A Machine Description Language for Compilation," Master's thesis, Dept. of ECE, UIUC, September 1994. [33] P. Paulin, C. Liem, T. May and S. Sutarwala, "FlexWare: A Flexible Firmware Development Environment for Embedded Systems," Code Generation for Embedded Processors, Kluwer Academic Publishers, 1995. [34] A. Inoue, H. Tomiyama, F. N. Eko, H. Kanbara, and H. Yasuura, "A Programming Language for Processor Based Embedded Systems," Proc. of APCHDL, 1998. [35] A. Inoue, H. Tomiyama, H. Okuma, H. Kanbara, and H. Yasuura, "Language and Compiler for Optimizing Datapath Widths of Embedded Systems," IEICE Trans. Fundamentals, E81-A(12):2595-2604, Dec. 1998. [36] A. Appel, J. Davidson, and N. Ramsey, "The Zephyr Compiler Infrastructure," Internal Report, http://www.RCS.virginia.edu/zephyr, 1998. [37] N. Ramsey and M. F. Fern¶andez, "Specifying Representations of Machine Instructions," ACM Trans. Programmming Languages and Systems, 19(3):492-524, May 1997. [38] N. Ramsey and J. W. Davidson, "Machine Descriptions to Build Tools for Embedded Systems," Proc. of LCTES, 1998. [39] M. W. Bailey and J. W. Davidson, "A Formal Model and Specification Languagefor Procedure Calling Conventions," Proc. of 22th POPL, 1995. [40] A. Halambi, P. Grun, V. Ganesh, A. Khare, N. Dutt, and A. Nicolau, "EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability," Proc. of DATE, 1999. [41] M. R. Hartoog, J. A. Rowson, P. D. Reddy, S. Desai, D. D. Dunlop, E. A. Harcourt, and N. Khullar, "Generation of Software Tools from Processor Descriptions for Hardware/Software Codesign," Proc. of 34th DAC, 1997.; http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/30767

Availability: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/30767

Using an Architectural Knowledge Base to Generate Code for Parallel Computers.

Authors: McGregor, John D. Riehl, Arthur M. Terrano, Anthony E. et al.

Source: Communications of the ACM; Sep89, Vol. 32 Issue 9, p1065-1072, 8p, 8 Diagrams

Subject Terms: PARALLEL computers, PROGRAMMING languages, ARTIFICIAL intelligence, COMPUTERS, COMPUTER software, SOURCE code

Code mapping algorithm for custom instructions on reconfigurable instruction set processors.

Authors: Zhang, Huizhen Chen, Yonghong

Source: International Journal of Electronics; Jan2015, Vol. 102 Issue 1, p18-31, 14p

Subject Terms: INSTRUCTION set processors, CARTOGRAPHY software, POLYNOMIALS, ALGORITHMS, PROGRAMMING languages

Elimination of Overhead Operations in Complex Loop Structures for Embedded Microprocessors.

Authors: Kavvadias, Nikolaos Nikolaidis, Spiridon

Source: IEEE Transactions on Computers; Feb2008, Vol. 57 Issue 2, p200-214, 15p, 2 Black and White Photographs, 6 Charts, 10 Graphs

Subject Terms: EMBEDDED computer systems, COMPUTERS, LOOP tiling (Computer science), MICROPROCESSORS, BENCHMARKING (Management), APPLICATION software

A Generative Programming Approach to Developing Pervasive Computing Systems

Authors: Cassou, Damien Bertran, Benjamin Loriant, Nicolas et al.

Contributors: Cassou, Damien Bertran, Benjamin Loriant, Nicolas et al.

Source: GPCE '09: Proceedings of the 8th international conference on Generative programming and component engineering ; https://hal.inria.fr/inria-00405819 ; GPCE '09: Proceedings of the 8th international conference on Generative programming and component engineering, Oct 2009, Denver, CO, United States. pp.137-146

Subject Terms: design, languages, pervasive computing, generative programming, DSL, diaspec, ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.11: Software Architectures/D.2.11.1: Domain-specific architectures, ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.11: Software Architectures/D.2.11.3: Languages (e.g., description, interconnection, definition), ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.11: Software Architectures/D.2.11.4: Patterns (e.g., client/server, pipeline, blackboard), ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.0: Code generation, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.9: Retargetable compilers, [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE], [INFO.INFO-IU]Computer Science [cs]/Ubiquitous Computing

Subject Geographic: Denver, CO, United States

Relation: inria-00405819; https://hal.inria.fr/inria-00405819; https://hal.inria.fr/inria-00405819v2/document; https://hal.inria.fr/inria-00405819v2/file/gpce42-cassou.pdf

Availability: https://hal.inria.fr/inria-00405819
https://hal.inria.fr/inria-00405819v2/document
https://hal.inria.fr/inria-00405819v2/file/gpce42-cassou.pdf

Computing Without Processors.

Source: Communications of the ACM; Aug2011, Vol. 54 Issue 8, p46-54, 9p, 1 Color Photograph, 11 Diagrams, 1 Graph

Subject Terms: COMPUTER programming, SYSTEMS development, COMPUTER multitasking, COMPUTER software, PROGRAMMING languages

Company/Entity: MICROSOFT Corp.

Efficient and retargetable SIMD translation in a dynamic binary translator.

Authors: Fu, Sheng‐Yu Hong, Ding‐Yong Liu, Yu‐Ping et al.

Source: Software: Practice & Experience; Jun2018, Vol. 48 Issue 6, p1312-1330, 19p

Subject Terms: SIMD (Computer architecture), PARALLEL computers, SVG (Document markup language), QUANTUM computing

Company/Entity: STANDARD Performance Evaluation Corp.

Synchronous Deterministic Parallel Programming for Multi-Cores with ForeC.

Authors: YIP, EUGENE GIRAULT, ALAIN ROOP, PARTHA S. et al.

Source: ACM Transactions on Programming Languages & Systems; Jun2023, Vol. 45 Issue 2, p1-74, 74p

Subject Terms: PARALLEL programming, MULTICORE processors, PROGRAMMING languages, PITFALL traps, DEBUGGING

Compilation for heterogeneous SoCs : bridging the gap between software and target-specific mechanisms

Authors: Dardaillon, Mickaël Marquet, Kevin Risset, Tanguy et al.

Contributors: Dardaillon, Mickaël Marquet, Kevin Risset, Tanguy et al.

Source: workshop on High Performance Energy Efficient Embedded Systems - HIPEAC ; https://inria.hal.science/hal-00936924 ; workshop on High Performance Energy Efficient Embedded Systems - HIPEAC, Jan 2014, Vienne, Austria

Subject Terms: Data-flow languages, Retargetable compilers, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.2: Language Classifications/D.3.2.3: Data-flow languages, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.9: Retargetable compilers, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

Subject Geographic: Vienne, Austria

Availability: https://inria.hal.science/hal-00936924
https://inria.hal.science/hal-00936924v1/document
https://inria.hal.science/hal-00936924v1/file/hip3es_submission_1.pdf

A Compilation Flow for Parametric Dataflow: Programming Model, Scheduling, and Application to Heterogeneous MPSoC

Authors: Dardaillon, Mickaël Marquet, Kevin Risset, Tanguy et al.

Contributors: Dardaillon, Mickaël Marquet, Kevin Risset, Tanguy et al.

Source: Proceedings of the ACM International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES) ; International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES) ; https://hal.science/hal-01048649 ; International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), Oct 2014, New Dehli, India. pp.1-10, ⟨10.1145/2656106.2656110⟩

Subject Terms: data flow, programming model, heterogeneous MPSoC, compiler, scheduling, D.3.2 [Programming Languages]: Language Classifications--Data-flow languages, D.3.3 [Programming Languages]: Processors--Retargetable compilers, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Subject Geographic: New Dehli, India

Availability: https://hal.science/hal-01048649
https://hal.science/hal-01048649v1/document
https://hal.science/hal-01048649v1/file/cases2014-final.pdf
https://doi.org/10.1145/2656106.2656110

Towards a Tool-based Development Methodology for Pervasive Computing Applications

Authors: Cassou, Damien Bruneau, Julien Consel, Charles et al.

Contributors: Cassou, Damien Bruneau, Julien Consel, Charles et al.

Source: ISSN: 0098-5589 ; IEEE Transactions on Software Engineering ; https://inria.hal.science/hal-00683210 ; IEEE Transactions on Software Engineering, 2012, 38 (6), pp.1445-1463. ⟨10.1109/TSE.2011.107⟩.

Subject Terms: diaspec, diasuite, Domain-Specific Language, Programming Support, Simulation, Methodology, Generative Programming, Pervasive Computing, Toolkit, ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.11: Software Architectures/D.2.11.1: Domain-specific architectures, ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.11: Software Architectures/D.2.11.3: Languages (e.g., description, interconnection, definition), ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.9: Retargetable compilers, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.0: Code generation, [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL], [INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE], [INFO.INFO-IU]Computer Science [cs]/Ubiquitous Computing

Relation: info:eu-repo/semantics/altIdentifier/arxiv/1203.6459; ARXIV: 1203.6459

Availability: https://inria.hal.science/hal-00683210
https://inria.hal.science/hal-00683210/document
https://inria.hal.science/hal-00683210/file/TSE-2010-06-0178.R3_Cassou.pdf
https://doi.org/10.1109/TSE.2011.107

Retargetable Code Generation Based on Structural Processor Description.

Authors: Leupers, Rainer Marwedel, Peter

Source: Design Automation for Embedded Systems; Jan1998, Vol. 3 Issue 1, p75-108, 34p

Writing retargetable parallel programs for low and high level vision using a global address space.

Authors: Dunn, S.M.

Source: 1990 Proceedings 10th International Conference on Pattern Recognition; 1990, Issue ii, p591-591, 1p

Infrastructures and Compilation Strategies for the Performance of Computing Systems

Authors: Rohou, Erven Amdahl's Law is Forever (ALF) Inria Rennes – Bretagne Atlantique et al.

Contributors: Rohou, Erven Amdahl's Law is Forever (ALF) Inria Rennes – Bretagne Atlantique et al.

Source: https://inria.hal.science/tel-01237164 ; Other [cs.OH]. Université de Rennes 1, 2015.

Subject Terms: optimization, JIT, interpreter, dynamic binary optimization, performance, compilation, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.4: Interpreters, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.0: Code generation, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.6: Optimization, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.9: Retargetable compilers, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.2: Multiple Data Stream Architectures (Multiprocessors)/C.1.2.7: Single-instruction-stream, multiple-data-stream processors (SIMD), ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.1: Single Data Stream Architectures/C.1.1.2: RISC/CISC, VLIW architectures, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.2: Multiple Data Stream Architectures (Multiprocessors)/C.1.2.6: Pipeline processors, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH]

Relation: info:eu-repo/grantAgreement//Esprit Project 22729/EU/Optimising Compilers for Embedded Applications/OCEANS; info:eu-repo/grantAgreement//33478/EU/Advanced Compiler Technologies for Embedded Streaming/ACOTES; info:eu-repo/grantAgreement/EC/FP7/214009/EU/Open Media Platform/OMP

Availability: https://inria.hal.science/tel-01237164
https://inria.hal.science/tel-01237164/document
https://inria.hal.science/tel-01237164/file/HDR-Erven-Rohou.pdf

RETARGETABLE COMPILER DESIGN ISSUES.

Authors: Korenkov, Iurii Loginov, Ivan Doronin, Oleg et al.

Source: Proceedings of the International Multidisciplinary Scientific GeoConference SGEM; 2019, Vol. 19 Issue 1, p561-568, 8p

Subject Terms: COMPILERS (Computer programs), PROGRAMMING languages, RESEARCH & development, ARCHITECTURE

Data Dependence Analysis of Assembly Code.

Authors: Amme, Wolfram Braun, Peter Thomasset, François et al.

Source: International Journal of Parallel Programming; Oct2000, Vol. 28 Issue 5, p431-467, 37p

Subject Terms: SOURCE code, COMPUTER software, ASSEMBLY languages (Electronic computers), PROGRAMMING languages, PARALLEL programming, COMPUTER programming, ALGORITHMS

SWARP: a retargetable preprocessor for multimedia instructions.

Authors: Pokam, Gilles Bihan, Stéphane Simonnet, Julien et al.

Source: Concurrency & Computation: Practice & Experience; Feb/Mar2004, Vol. 16 Issue 2/3, p303-318, 16p, 4 Diagrams, 1 Graph

Subject Terms: COMPILERS (Computer programs), COMPUTER systems, MULTIMEDIA systems, MULTIMEDIA communications, MICROPROCESSORS, SYSTEMS software, EMBEDDED computer systems

Rubus: A compiler for seamless and extensible parallelism.

Authors: Adnan, Muhammad Aslam, Faisal Nawaz, Zubair et al.

Source: PLoS ONE; 12/06/2017, Vol. 12 Issue 12, p1-23, 23p

Subject Terms: COMPILERS (Computer programs), 3-D computer games, GRAPHICS processing units, PROGRAMMING languages, PARALLEL programming