Search Results - ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.0: Code generation

Minimal Unroll Factor for Code Generation of Software Pipelining

Authors: Bachir, Mounira Touati, Sid Frédéric, Brault et al.

Contributors: Bachir, Mounira Touati, Sid Frédéric, Brault et al.

Source: ISSN: 0885-7458.

Subject Terms: Periodic register allocation, Software pipelining, Code generation, Instruction level parallelism, Embedded systems, Compilation, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.0: Code generation, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.6: Optimization, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-PF]Computer Science [cs]/Performance [cs.PF]

Availability: https://inria.hal.science/hal-00764521
https://inria.hal.science/hal-00764521v1/document
https://inria.hal.science/hal-00764521v1/file/mainSubmitMinPPCMJounal.pdf
https://doi.org/10.1007/s10766-012-0203-z

Compiler Mitigations for Time Attacks on Modern x86 Processors

Authors: Jeroen Van Cleemput Bart Coppens Bjorn De Sutter et al.

Contributors: Jeroen Van Cleemput Bart Coppens Bjorn De Sutter et al.

Source: http://users.elis.ugent.be/~brdsutte/research/publications/2012TACOvancleemput.pdf.

Subject Terms: Categories and Subject Descriptors, D.2.0 [Software Engineering, General—Protection mechanisms, D.3.4 [Programming Languages, Processors—Code generation, compilers, optimization General Terms, Experimentation, Measurement, Security Additional Key Words and Phrases, Time-based side channels, x86 architecture, variable latency instructions ACM Reference Format

File Description: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.306.7302; http://users.elis.ugent.be/~brdsutte/research/publications/2012TACOvancleemput.pdf

Availability: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.306.7302
http://users.elis.ugent.be/~brdsutte/research/publications/2012TACOvancleemput.pdf

Speculatively Vectorized Bytecode

Authors: Rohou, Erven Dyshel, Sergei Nuzman, Dorit et al.

Contributors: Rohou, Erven Dyshel, Sergei Nuzman, Dorit et al.

Source: International Conference on High-Performance and Embedded Architectures and Compilers ; https://inria.hal.science/inria-00525139 ; International Conference on High-Performance and Embedded Architectures and Compilers, Manolis Katevenis and Margaret Martonosi, Jan 2011, Heraklion, Greece

Subject Terms: ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.2: Multiple Data Stream Architectures (Multiprocessors)/C.1.2.7: Single-instruction-stream, multiple-data-stream processors (SIMD), ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.13: Reusable Software, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.0: Code generation, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.6: Optimization, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH]

Subject Geographic: Heraklion, Greece

Relation: info:eu-repo/grantAgreement//26535/EU/High-Performance Embedded Architectures and Compilers/HIPEAC

Availability: https://inria.hal.science/inria-00525139
https://inria.hal.science/inria-00525139/document
https://inria.hal.science/inria-00525139/file/Rohou-HiPEAC11.pdf

An Optimization Framework for Embedded Processors with Auto-Addressing Mode.

Authors: XIAOTONG ZHUANG PANDE, SANTOSH

Source: ACM Transactions on Programming Languages & Systems; Apr2010, Vol. 32 Issue 4, p11-11.41, 41p, 10 Diagrams, 8 Charts, 9 Graphs

Subject Terms: EMBEDDED computer systems, SERVICE-oriented architecture (Computer science), DIGITAL signal processing, PROGRAMMING languages, COMPUTER programming, COMPUTER software

Halide: Decoupling Algorithms from Schedules for High-Performance Image Processing.

Authors: Ragan-Kelley, Jonathan Adams, Andrew Sharlet, Dillon et al.

Source: Communications of the ACM; Jan2018, Vol. 61 Issue 1, p106-115, 10p, 3 Diagrams, 1 Graph

Subject Terms: MATHEMATICAL decoupling, ALGORITHMS, IMAGE processing, COMPUTER scheduling, HIGH performance processors, COMPUTER vision, PROGRAMMING languages, COMPUTATIONAL photography, MATHEMATICS

Code mapping algorithm for custom instructions on reconfigurable instruction set processors.

Authors: Zhang, Huizhen Chen, Yonghong

Source: International Journal of Electronics; Jan2015, Vol. 102 Issue 1, p18-31, 14p

Subject Terms: INSTRUCTION set processors, CARTOGRAPHY software, POLYNOMIALS, ALGORITHMS, PROGRAMMING languages

Intermediate Representations for Explicitly Parallel Programs.

Authors: SUSUNGI, ADILLA TADONKI, CLAUDE

Source: ACM Computing Surveys; Jun2022, Vol. 54 Issue 5, p1-24, 24p

Subject Terms: PROGRAMMING languages, MULTICORE processors, PARALLEL programming, COMPILERS (Computer programs)

Tag-Protector: An Effective and Dynamic Detection of Illegal Memory Accesses through Compile Time Code Instrumentation.

Authors: Saeed, Ahmed Ahmadinia, Ali Just, Mike

Source: Advances in Software Engineering; 6/19/2016, p1-19, 19p

Subject Terms: PROGRAMMING languages, COMPUTER security vulnerabilities, COMPUTER storage devices, C++, SOURCE code, RUN time systems (Computer science), MULTICORE processors

Using an Architectural Knowledge Base to Generate Code for Parallel Computers.

Authors: McGregor, John D. Riehl, Arthur M. Terrano, Anthony E. et al.

Source: Communications of the ACM; Sep89, Vol. 32 Issue 9, p1065-1072, 8p, 8 Diagrams

Subject Terms: PARALLEL computers, PROGRAMMING languages, ARTIFICIAL intelligence, COMPUTERS, COMPUTER software, SOURCE code

SAC—A Functional Array Language for Efficient Multi-threaded Execution.

Authors: Grelck, Clemens Scholz, Sven-Bodo

Source: International Journal of Parallel Programming; Aug2006, Vol. 34 Issue 4, p383-427, 45p, 13 Diagrams, 2 Charts

Subject Terms: PROGRAMMING languages, ARRAY processors, PROGRAMMABLE array logic, PARALLEL processing, COMPUTER software, AUTOMATION, COMPUTER architecture, SOURCE code, DATA flow computing

Static strands: Safely exposing dependence chains for increasing embedded power efficiency

Authors: Peter G. Sassone D. Scott Wills Gabriel H. Loh et al.

Contributors: Peter G. Sassone D. Scott Wills Gabriel H. Loh et al.

Source: http://peter.wreck.org/prof/2007_SASSONE_TECS.pdf.

Subject Terms: Categories and Subject Descriptors, C.1.1 [Processor Architectures, Single Data Stream Architectures, D.3.4 [Programming Languages, Processors–Code Generation, Optimization General Terms, Performance, Design Additional Key Words and Phrases, Architecture, sequentiality, dependency collapsing, energy ACM Reference Format

File Description: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.104.1994; http://peter.wreck.org/prof/2007_SASSONE_TECS.pdf

Availability: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.104.1994
http://peter.wreck.org/prof/2007_SASSONE_TECS.pdf

7Scaling Performance via Self-Tuning Approximation for Graphics Engines

Authors: Mehrzad Samadi Janghaeng Lee D. Anoushe Jamshidi et al.

Contributors: Mehrzad Samadi Janghaeng Lee D. Anoushe Jamshidi et al.

Source: http://cccp.eecs.umich.edu/papers/samadi-tocs14.pdf.

Subject Terms: Categories and Subject Descriptors, D.3.4 [Programming Languages, Processors—Code generation, Compilers General Terms, Design, Performance Additional Key Words and Phrases, Approximate computing, compiler, GPU, optimization ACM Reference Format

File Description: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.501.1708

Availability: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.501.1708
http://cccp.eecs.umich.edu/papers/samadi-tocs14.pdf

Abstraction of RTL IPs into Embedded Software.

Authors: Bombieri, Nicola Fummi, Franco Pravadelli, Graziano

Source: DAC: Annual ACM/IEEE Design Automation Conference; Jun2010, p24-29, 6p, 5 Diagrams, 1 Chart, 1 Graph

Subject Terms: INTEGRATED circuits, INTEGRATED circuit design, HIGH performance processors, INTERNET protocols, ALGORITHM software, PROGRAMMING languages

VeCoGen: Automating Generation of Formally Verified C Code With Large Language Models

Authors: Sevenhuijsen, Merlijn Etemadi, Khashayar Nyberg, Mattias

Source: FormaliSE 2025: ACM/IEEE International Conference on Formal Methods in Software Engineering, Ottawa, Canada, April , 2025..

Subject Terms: Codes, Program processors, Limiting, Large language models, Natural languages, Programming, Specification languages, Formal specifications, Formal verification, Software development management, Datalogi, Computer Science

File Description: print

Access URL: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-364661

Large language models for G-code generation in CNC machining: A comparison of ChatGPT-3.5 and ChatGPT-4o.

Authors: Šket, K. Potočnik, D. Brezocnik, M. et al.

Source: Advances in Production Engineering & Management; Jun2025, Vol. 20 Issue 2, p224-238, 15p

Subject Terms: LANGUAGE models, MACHINING, PROGRAMMING languages, MANUFACTURING processes, STANDARDS, GENERATIVE pre-trained transformers

Company/Entity: OPENAI Inc.

Computing Without Processors.

Source: Communications of the ACM; Aug2011, Vol. 54 Issue 8, p46-54, 9p, 1 Color Photograph, 11 Diagrams, 1 Graph

Subject Terms: COMPUTER programming, SYSTEMS development, COMPUTER multitasking, COMPUTER software, PROGRAMMING languages

Company/Entity: MICROSOFT Corp.

c○ACM. Integrated Code Generation for Loops

Authors: Mattias Eriksson Christoph Kessler Linköping University et al.

Contributors: Mattias Eriksson Christoph Kessler Linköping University et al.

Source: http://www.ida.liu.se/%7Echrke/papers/Eriksson-Kessler-ACM-TECS-2012-manuscript.pdf.

Subject Terms: Categories and Subject Descriptors, D.3.4 [Programming Languages, Processors—Code Generation, Optimization General Terms, Algorithms, Experimentation, Performance, Theory Additional Key Words and Phrases, Code generation, clustered VLIW architectures, modulo

File Description: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.261.1987

Availability: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.261.1987
http://www.ida.liu.se/%7Echrke/papers/Eriksson-Kessler-ACM-TECS-2012-manuscript.pdf

Combining Functional and Imperative Programming for Multicore Software: An Empirical Study Evaluating Scala and Java.

Authors: Pankratius, Victor Schmidt, Felix Garretón, Gilda

Source: ICSE: International Conference on Software Engineering; Feb2012, p123-133, 11p

Subject Terms: COMPUTER programming, PROGRAMMING languages, JAVA programming language, COMPUTER software development, MULTICORE processors, SOFTWARE engineering, ELECTRONIC data processing

MAXIMUM PIPELINING OF ARRAY COMPUTATION: A PIPELINED CODE MAPPING SCHEME FOR DATAFLOW COMPUTERS.

Authors: Gao, Guang R.

Source: INFOR; May89, Vol. 27 Issue 2, p145-172, 28p

Subject Terms: DATA flow computing, PIPELINE computers, ARRAY processors, CODING theory, COMPUTER programming, PROGRAMMING languages, COMPUTER software development, MATHEMATICAL optimization

Compilation of Stream Programs onto Scratchpad Memory Based Embedded Multicore Processors Through Retiming.

Authors: Weijia Che Chatha, Karam

Source: DAC: Annual ACM/IEEE Design Automation Conference; Jun2011, p122-127, 6p, 3 Diagrams, 2 Charts, 5 Graphs

Subject Terms: STREAMING technology, MULTICORE processors, MICROPROCESSORS, SIGNAL processing, NETWORK processors, PROGRAMMING languages, BUFFER storage (Computer science)