Search Results - ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.2: Design Aids
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Source: the RISC-V Week ; https://hal.sorbonne-universite.fr/hal-02316711 ; the RISC-V Week, Oct 2019, Paris, France
Subject Terms: ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.2: Design Aids, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.2: Design Aids, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.5: Microprocessors and microcomputers, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.2: Design Aids/B.7.2.2: Placement and routing, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [SPI.TRON]Engineering Sciences [physics]/Electronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Availability: https://hal.sorbonne-universite.fr/hal-02316711
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Source: ISSN: 1546-1998 ; Journal of Low Power Electronics ; https://inria.hal.science/hal-00747721 ; Journal of Low Power Electronics, 2011, 7 (4), pp.482-489. ⟨10.1166/jolpe.2011.1159⟩.
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Authors: et al.
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Source: Free Silicon Conference ; https://hal.sorbonne-universite.fr/hal-02316744 ; Free Silicon Conference, LIP6, Mar 2019, Paris, France
Subject Terms: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.2: Design Aids, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [SPI.TRON]Engineering Sciences [physics]/Electronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Availability: https://hal.sorbonne-universite.fr/hal-02316744
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Subject Terms: Categories and Subject Descriptors, B.7.2 [Hardware, Integrated Circuits, Design Aids, Placement and Routing General Terms, Design, Algorithms, Performance Additional Key Words and Phrases, Floorplanning, placement, geometry constraint, mixed-size design ACM Reference Format
File Description: application/pdf
Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.649.817; http://home.eng.iastate.edu/~cnchu/pubs/j53.pdf
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Contributors: The Pennsylvania State University CiteSeerX Archives
Source: http://eda.ee.ucla.edu/pub/J68.pdf.
Subject Terms: Categories and Subject Descriptors, B.7.2 [Hardware, Integrated Circuits—Design Aids General Terms, Design, Algorithms, Performance Additional Key Words and Phrases, Yield analysis, Circuit simulation, Monte Carlo, Yield optimization. ACM Reference Format
File Description: application/pdf
Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.381.4704; http://eda.ee.ucla.edu/pub/J68.pdf
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Authors: et al.
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Source: http://eda.ee.ucla.edu/pub/J70.pdf.
Subject Terms: Categories and Subject Descriptors, B.7.2 [Hardware, Integrated Circuits—Design aids General Terms, Design Additional Key Words and Phrases, Timing, leakage, yield estimation, FPGA architecture ACM Reference Format
File Description: application/pdf
Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.381.5432; http://eda.ee.ucla.edu/pub/J70.pdf
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7
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Source: https://inria.hal.science/inria-00311300 ; [Research Report] RR-6615, INRIA. 2008, pp.46.
Subject Terms: ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.1: Design Styles/B.6.1.5: Parallel circuits, ACM: B.: Hardware/B.8: PERFORMANCE AND RELIABILITY/B.8.2: Performance Analysis and Design Aids, ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.5: Model Development/I.6.5.0: Modeling methodologies, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS/C.3.2: Real-time and embedded systems, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]
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Authors: et al.
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Source: https://inria.hal.science/inria-00482035 ; [Research Report] RR-7281, INRIA. 2010, pp.19.
Subject Terms: High-level synthesis, hardware accelerators, DDR-SDRAM, optimized communications, program transformation, reconfigurable architectures, FPGA, ACM: B.: Hardware/B.4: INPUT/OUTPUT AND DATA COMMUNICATIONS/B.4.1: Data Communications Devices/B.4.1.0: Processors, ACM: B.: Hardware/B.4: INPUT/OUTPUT AND DATA COMMUNICATIONS/B.4.2: Input/Output Devices/B.4.2.0: Channels and controllers, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.1: Algorithms implemented in hardware, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.3: Input/output circuits, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.0: Adaptable architectures, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL]
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Authors: et al.
Source: ACM Transactions on Embedded Computing Systems; May2023, Vol. 22 Issue 3, p1-30, 30p
Subject Terms: MACHINE learning, PARTICIPATORY design, CONVOLUTIONAL neural networks, SHARED workspaces, APPLICATION-specific integrated circuits, ARCHITECTURAL design
Company/Entity: NATIONAL Basketball Association
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Source: ISSN: 2199-2002 ; Leibniz Transactions on Embedded Systems ; https://hal.inria.fr/hal-02303635 ; Leibniz Transactions on Embedded Systems, European Design and Automation Association (EDAA) \ EMbedded Systems Special Interest Group (EMSIG) and Schloss Dagstuhl -- Leibniz-Zentrum für Informatik GmbH, Dagstuhl Publishing., 2018.
Subject Terms: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.3: Reliability and Testing/B.7.3.2: Redundant design, ACM: F.: Theory of Computation/F.3: LOGICS AND MEANINGS OF PROGRAMS/F.3.2: Semantics of Programming Languages/F.3.2.5: Program analysis, [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]
Relation: hal-02303635; https://hal.inria.fr/hal-02303635
Availability: https://hal.inria.fr/hal-02303635
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Source: 13th International Workshop on Worst-Case Execution Time Analysis
https://inria.hal.science/hal-00909330
13th International Workshop on Worst-Case Execution Time Analysis, Jul 2013, Paris, France. pp.21-31, ⟨10.4230/OASIcs.WCET.2013.i⟩Subject Terms: WCET estimation, multicore architecture, parallel programming, ACM: B.: Hardware/B.8: PERFORMANCE AND RELIABILITY/B.8.2: Performance Analysis and Design Aids, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS, ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.4: Software/Program Verification, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]
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Contributors: The Pennsylvania State University CiteSeerX Archives
Subject Terms: Categories and Subject Descriptors B.7.2 [Hardware, Integrated Circuits, Design Aids, Placement routing. General Terms, Algorithms, Design. Keywords, Timing Driven Placement, Force Directed Placement, Net Constraints
File Description: application/pdf
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Authors: et al.
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Source: https://inria.hal.science/inria-00381644 ; [Research Report] RR-6919, INRIA. 2009, pp.19.
Subject Terms: FIFO sizing, Buffer sizing, Throughput, Latency-Insensitive Design, Marked Graphs, ACM: F.: Theory of Computation/F.1: COMPUTATION BY ABSTRACT DEVICES/F.1.1: Models of Computation, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS, [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]
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14
Authors: et al.
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Subject Terms: General Terms Algorithms, Performance, Design Keywords Chip Multi-Processor, High-Level Design
File Description: application/pdf
Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.83.8437; http://www.stanford.edu/~wachs/pubs/dac_2007.pdf
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15
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Subject Terms: General Terms Algorithms, Performance, Design Keywords Leakage currents, Threshold voltage, Mixed Gates, Gate leakage
File Description: application/pdf
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Source: http://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/2003/dac03/pdffiles/21_2.pdf.
File Description: application/pdf
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Source: IEEE International Symposium on Circuits and Systems ; https://inria.hal.science/hal-00931036 ; IEEE International Symposium on Circuits and Systems, Jun 2014, Melbourne, Australia
Subject Terms: custom operator, DFG, subgraph enumeration algorithm, subgraph selection algorithm, high-level synthesis, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.2: Design Aids, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]
Availability: https://inria.hal.science/hal-00931036
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Subject Terms: General Terms Algorithms, Performance Keywords Leakage currents, threshold voltage, MVT
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File Description: application/postscript
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Source: ACM Transactions on Embedded Computing Systems; May2013 Supplement 2, Vol. 12, p1-26, 26p
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