Suchergebnisse - ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types AND Design Styles/B.7.1.2: Gate arrays*
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Autoren: et al.
Weitere Verfasser: et al.
Quelle: ARC 2017 - 13th International Symposium on Applied Reconfigurable Computing ; https://hal.science/hal-01475251 ; ARC 2017 - 13th International Symposium on Applied Reconfigurable Computing, Delft University of Technology Apr 2017, Delft, Netherlands ; http://www.arc2017.tudelft.nl
Schlagwörter: Reconfigurable cores, ACM: B.: Hardware, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.1: Design, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.2: Gate arrays, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.7: VLSI (very large scale integration), ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.11: Software Architectures/D.2.11.4: Patterns (e.g., client/server, pipeline, blackboard), [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]
Geographisches Schlagwort: Delft, Netherlands
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2
Autoren: et al.
Weitere Verfasser: et al.
Quelle: ARC 2017 - 13th International Symposium on Applied Reconfigurable Computing ; https://hal.science/hal-01475251 ; ARC 2017 - 13th International Symposium on Applied Reconfigurable Computing, Delft University of Technology Apr 2017, Delft, Netherlands ; http://www.arc2017.tudelft.nl
Schlagwörter: Reconfigurable cores, ACM: B.: Hardware, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.1: Design, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.2: Gate arrays, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.7: VLSI (very large scale integration), ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.11: Software Architectures/D.2.11.4: Patterns (e.g., client/server, pipeline, blackboard), [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]
Geographisches Schlagwort: Delft, Netherlands
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Autoren: et al.
Weitere Verfasser: et al.
Quelle: ARC 2017 - 13th International Symposium on Applied Reconfigurable Computing ; https://hal.science/hal-01475251 ; ARC 2017 - 13th International Symposium on Applied Reconfigurable Computing, Delft University of Technology Apr 2017, Delft, Netherlands ; http://www.arc2017.tudelft.nl
Schlagwörter: Reconfigurable cores, ACM: B.: Hardware, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.1: Design, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.2: Gate arrays, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.7: VLSI (very large scale integration), ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.11: Software Architectures/D.2.11.4: Patterns (e.g., client/server, pipeline, blackboard), [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]
Geographisches Schlagwort: Delft, Netherlands
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Autoren: et al.
Weitere Verfasser: et al.
Quelle: ARC 2017 - 13th International Symposium on Applied Reconfigurable Computing ; https://hal.science/hal-01475251 ; ARC 2017 - 13th International Symposium on Applied Reconfigurable Computing, Delft University of Technology Apr 2017, Delft, Netherlands ; http://www.arc2017.tudelft.nl
Schlagwörter: Reconfigurable cores, ACM: B.: Hardware, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.1: Design, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.2: Gate arrays, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.7: VLSI (very large scale integration), ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.11: Software Architectures/D.2.11.4: Patterns (e.g., client/server, pipeline, blackboard), [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]
Geographisches Schlagwort: Delft, Netherlands
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Autoren: et al.
Weitere Verfasser: et al.
Quelle: ARC 2017 - 13th International Symposium on Applied Reconfigurable Computing ; https://hal.science/hal-01475251 ; ARC 2017 - 13th International Symposium on Applied Reconfigurable Computing, Delft University of Technology Apr 2017, Delft, Netherlands ; http://www.arc2017.tudelft.nl
Schlagwörter: Reconfigurable cores, ACM: B.: Hardware, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.1: Design, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.2: Gate arrays, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.7: VLSI (very large scale integration), ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.11: Software Architectures/D.2.11.4: Patterns (e.g., client/server, pipeline, blackboard), [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]
Geographisches Schlagwort: Delft, Netherlands
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6
Autoren: et al.
Weitere Verfasser: et al.
Quelle: ARC 2017 - 13th International Symposium on Applied Reconfigurable Computing ; https://hal.science/hal-01475251 ; ARC 2017 - 13th International Symposium on Applied Reconfigurable Computing, Delft University of Technology Apr 2017, Delft, Netherlands ; http://www.arc2017.tudelft.nl
Schlagwörter: Reconfigurable cores, ACM: B.: Hardware, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.1: Design, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.2: Gate arrays, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.7: VLSI (very large scale integration), ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.11: Software Architectures/D.2.11.4: Patterns (e.g., client/server, pipeline, blackboard), [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]
Geographisches Schlagwort: Delft, Netherlands
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Autoren: et al.
Weitere Verfasser: et al.
Quelle: FCCM - 23rd IEEE International Symposium on Field-Programmable Custom Computing Machines ; https://inria.hal.science/hal-01140008 ; FCCM - 23rd IEEE International Symposium on Field-Programmable Custom Computing Machines, May 2015, Vancouver, Canada. ⟨10.1109/FCCM.2015.55⟩ ; http://fccm.org/2015/
Schlagwörter: AES algorithm, FPGA, Hardware trojan, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.2: Gate arrays, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]
Geographisches Schlagwort: Vancouver
Time: Vancouver, Canada
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Autoren: et al.
Weitere Verfasser: et al.
Quelle: FCCM - 23rd IEEE International Symposium on Field-Programmable Custom Computing Machines ; https://hal.inria.fr/hal-01140008 ; FCCM - 23rd IEEE International Symposium on Field-Programmable Custom Computing Machines, May 2015, Vancouver, Canada. ⟨10.1109/FCCM.2015.55⟩ ; http://fccm.org/2015/
Schlagwörter: Hardware trojan, FPGA, AES algorithm, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.2: Gate arrays, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]
Geographisches Schlagwort: Vancouver
Time: Vancouver, Canada
Relation: hal-01140008; https://hal.inria.fr/hal-01140008; https://hal.inria.fr/hal-01140008/document; https://hal.inria.fr/hal-01140008/file/swierczynski-fccm15.pdf
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Autoren: et al.
Weitere Verfasser: et al.
Quelle: FPL - 24th International Conference on Field Programmable Logic and Applications ; https://inria.hal.science/hal-01017184 ; FPL - 24th International Conference on Field Programmable Logic and Applications, Sep 2014, Munich, Germany. ⟨10.1109/FPL.2014.6927494⟩
Schlagwörter: Partial reconfiguration, FPGA, heterogeneous fixed-function blocks, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.2: Gate arrays, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]
Relation: info:eu-repo/grantAgreement/EC/FP7/288248/EU/Self adaptive heterogeneous manycore based on Flexible Tiles/FLEXTILES
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Autoren: et al.
Weitere Verfasser: et al.
Quelle: FPL - 24th International Conference on Field Programmable Logic and Applications ; https://inria.hal.science/hal-01017184 ; FPL - 24th International Conference on Field Programmable Logic and Applications, Sep 2014, Munich, Germany. ⟨10.1109/FPL.2014.6927494⟩
Schlagwörter: Partial reconfiguration, FPGA, heterogeneous fixed-function blocks, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.2: Gate arrays, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]
Relation: info:eu-repo/grantAgreement/EC/FP7/288248/EU/Self adaptive heterogeneous manycore based on Flexible Tiles/FLEXTILES
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Autoren: et al.
Weitere Verfasser: et al.
Quelle: FPL - 24th International Conference on Field Programmable Logic and Applications ; https://inria.hal.science/hal-01017184 ; FPL - 24th International Conference on Field Programmable Logic and Applications, Sep 2014, Munich, Germany. ⟨10.1109/FPL.2014.6927494⟩
Schlagwörter: Partial reconfiguration, FPGA, heterogeneous fixed-function blocks, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.2: Gate arrays, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]
Relation: info:eu-repo/grantAgreement/EC/FP7/288248/EU/Self adaptive heterogeneous manycore based on Flexible Tiles/FLEXTILES
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Autoren: et al.
Weitere Verfasser: et al.
Quelle: FPL - 24th International Conference on Field Programmable Logic and Applications ; https://hal.inria.fr/hal-01017184 ; FPL - 24th International Conference on Field Programmable Logic and Applications, Sep 2014, Munich, Germany. ⟨10.1109/FPL.2014.6927494⟩
Schlagwörter: Partial reconfiguration, FPGA, heterogeneous fixed-function blocks, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.2: Gate arrays, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]
Relation: info:eu-repo/grantAgreement/EC/FP7/288248/EU/Self adaptive heterogeneous manycore based on Flexible Tiles/FLEXTILES; hal-01017184; https://hal.inria.fr/hal-01017184; https://hal.inria.fr/hal-01017184/document; https://hal.inria.fr/hal-01017184/file/huriaux-fpl14.pdf
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Autoren: et al.
Weitere Verfasser: et al.
Quelle: FPL - 24th International Conference on Field Programmable Logic and Applications ; https://inria.hal.science/hal-01017184 ; FPL - 24th International Conference on Field Programmable Logic and Applications, Sep 2014, Munich, Germany. ⟨10.1109/FPL.2014.6927494⟩
Schlagwörter: Partial reconfiguration, FPGA, heterogeneous fixed-function blocks, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.2: Gate arrays, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], info, archi
Relation: https://inria.hal.science/hal-01017184/file/huriaux-fpl14.pdf; https://inria.hal.science/hal-01017184
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