Suchergebnisse - ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids

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  1. 1

    A Polynomial Based Approach to Wakeup Time and Energy Estimation in Power-Gated Logic Clusters

    Autoren: D. Tovinakere, Vivek Sentieys, Olivier Derrien, Steven et al.

    Weitere Verfasser: D. Tovinakere, Vivek Sentieys, Olivier Derrien, Steven et al.

    Quelle: ISSN: 1546-1998 ; Journal of Low Power Electronics ; https://inria.hal.science/hal-00747721 ; Journal of Low Power Electronics, 2011, 7 (4), pp.482-489. ⟨10.1166/jolpe.2011.1159⟩.

    Schlagwörter: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.2: Design Aids, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Verfügbarkeit: https://inria.hal.science/hal-00747721
    https://doi.org/10.1166/jolpe.2011.1159

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  2. 2

    Model Driven Engineering Benefits for High Level Synthesis

    Autoren: Le Beux, Sébastien Marquet, Philippe Dekeyser, Jean-Luc et al.

    Weitere Verfasser: Le Beux, Sébastien Marquet, Philippe Dekeyser, Jean-Luc et al.

    Quelle: https://inria.hal.science/inria-00311300 ; [Research Report] RR-6615, INRIA. 2008, pp.46.

    Schlagwörter: ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.1: Design Styles/B.6.1.5: Parallel circuits, ACM: B.: Hardware/B.8: PERFORMANCE AND RELIABILITY/B.8.2: Performance Analysis and Design Aids, ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.5: Model Development/I.6.5.0: Modeling methodologies, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS/C.3.2: Real-time and embedded systems, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Verfügbarkeit: https://inria.hal.science/inria-00311300
    https://inria.hal.science/inria-00311300/document
    https://inria.hal.science/inria-00311300/file/RR-6615.pdf

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  3. 3

    FPGA-Specific Synthesis of Loop-Nests with Pipelined Computational Cores

    Autoren: Alias, Christophe Pasca, Bogdan Plesco, Alexandru et al.

    Weitere Verfasser: Alias, Christophe Pasca, Bogdan Plesco, Alexandru et al.

    Quelle: https://inria.hal.science/inria-00606977 ; [Research Report] RR-7674, INRIA. 2011, pp.33.

    Schlagwörter: High-Level Synthesis, Compiler, ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES/B.2.4: High-Speed Arithmetic, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS/C.3.3: Signal processing systems, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL], [INFO.INFO-IA]Computer Science [cs]/Computer Aided Engineering, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

    Verfügbarkeit: https://inria.hal.science/inria-00606977
    https://inria.hal.science/inria-00606977v1/document
    https://inria.hal.science/inria-00606977v1/file/RR-7674.pdf

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  4. 4

    Smart Vision Chip for colon exploration ; Smart Vision Chip pour l’exploration du colon

    Autoren: Chuquimia, Orlando Systèmes Electroniques (SYEL) LIP6 et al.

    Weitere Verfasser: Chuquimia, Orlando Systèmes Electroniques (SYEL) LIP6 et al.

    Quelle: https://tel.archives-ouvertes.fr/tel-02494557 ; Imagerie médicale. Sorbonne Université, 2019. Français.

    Schlagwörter: Automatic polyp detection, intelligent endoscopic capsule, Hough transform, fuzzy trees, fuzzy forest, artificial vision and hardware accelerator, vision artificielle et accélérateur matériel, Détection automatique des polypes, capsule endoscopique intelligente, transformée d’Hough, arbres flous, forets floues, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: C.: Computer Systems Organization/C.5: COMPUTER SYSTEM IMPLEMENTATION, ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE/I.2.6: Learning, ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE/I.2.9: Robotics, ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE/I.2.10: Vision and Scene Understanding, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.7: Feature Measurement/I.4.7.5: Texture, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.0: General/I.4.0.1: Image processing software, [INFO.INFO-IM]Computer Science [cs]/Medical Imaging, [INFO.INFO-CV]Computer Science [cs]/Computer Vision and Pattern Recognition [cs.CV], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI], [INFO.INFO-RB]Computer Science [cs]/Robotics [cs.RO]

    Relation: tel-02494557; https://tel.archives-ouvertes.fr/tel-02494557; https://tel.archives-ouvertes.fr/tel-02494557/document; https://tel.archives-ouvertes.fr/tel-02494557/file/thhese_archivage__N%C2%B0dossier.pdf

    Verfügbarkeit: https://tel.archives-ouvertes.fr/tel-02494557
    https://tel.archives-ouvertes.fr/tel-02494557/document
    https://tel.archives-ouvertes.fr/tel-02494557/file/thhese_archivage__N%C2%B0dossier.pdf

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  5. 5

    Formal Methods for Schedulings of Latency-Insensitive Designs

    Autoren: Boucaron, Julien Millo, Jean-Vivien de Simone, Robert et al.

    Weitere Verfasser: Boucaron, Julien Millo, Jean-Vivien de Simone, Robert et al.

    Quelle: https://inria.hal.science/inria-00137495 ; [Research Report] RR-6149, INRIA. 2007, pp.25.

    Schlagwörter: repetitive cyclic scheduling, formal models, synchronous languages, digital circuits, latency insensitive designs, Systems-on-chip, electronic system-level design, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids, ACM: C.: Computer Systems Organization/C.4: PERFORMANCE OF SYSTEMS, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.2: Design Aids, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation, [INFO.INFO-RO]Computer Science [cs]/Operations Research [math.OC], [INFO.INFO-SC]Computer Science [cs]/Symbolic Computation [cs.SC]

    Verfügbarkeit: https://inria.hal.science/inria-00137495
    https://inria.hal.science/inria-00137495v2/document
    https://inria.hal.science/inria-00137495v2/file/RR-6149.pdf

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  6. 6

    HARDWARE AIDS FOR AUTOMATA DESIGN

    Autoren: Reilly, Norman B RAND CORP SANTA MONICA CA

    Weitere Verfasser: Reilly, Norman B RAND CORP SANTA MONICA CA

    Quelle: DTIC AND NTIS

    Schlagwörter: Computer Hardware, Bionics, BIONICS, AUTOMATA, CIRCUITS, COMPUTER LOGIC, COMPUTERS, CONTROL SYSTEMS, MATHEMATICAL MODELS, NERVE CELLS, NERVOUS SYSTEM

    Dateibeschreibung: text/html

    Relation: http://www.dtic.mil/docs/citations/AD0646393

    Verfügbarkeit: http://www.dtic.mil/docs/citations/AD0646393
    http://oai.dtic.mil/oai/oai?&verb=getRecord&metadataPrefix=html&identifier=AD0646393

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  7. 7

    Coverage Directed Test Generation automated by Machine Learning – A Review 1

    Autoren: C. Ioannides K. I. Eder The Pennsylvania State University CiteSeerX Archives

    Weitere Verfasser: C. Ioannides K. I. Eder The Pennsylvania State University CiteSeerX Archives

    Quelle: http://www.cs.bris.ac.uk/Publications/Papers/2001405.pdf.

    Schlagwörter: Categories and Subject Descriptors, B.5.2 [Hardware] – Design Aids – Verification. B.5.3 [Hardware] – Reliability and Testing – Test Ge, Parameter Learning General Terms, Design, Verification, Learning Additional Key Words and Phrases, Coverage Directed test Generation (CDG, Genetic Algorithms, Genetic Programming, Inductive Logic Programming (ILP, Bayesian Networks, Markov Models ACM File Format

    Dateibeschreibung: application/pdf

    Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.307.4520; http://www.cs.bris.ac.uk/Publications/Papers/2001405.pdf

    Verfügbarkeit: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.307.4520
    http://www.cs.bris.ac.uk/Publications/Papers/2001405.pdf

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  8. 8

    ARMHEx: A hardware extension for DIFT on ARM-based SoCs

    Autoren: Wahab, Muhammad Abdul Cotret, Pascal Nasr Allah, Mounir et al.

    Weitere Verfasser: Wahab, Muhammad Abdul Cotret, Pascal Nasr Allah, Mounir et al.

    Quelle: 2017 27th International Conference on Field Programmable Logic and Applications (FPL)
    https://hal.science/hal-01558473
    2017 27th International Conference on Field Programmable Logic and Applications (FPL), Sep 2017, Ghent, Belgium. ⟨10.23919/fpl.2017.8056767⟩
    https://www.fpl2017.org/

    Schlagwörter: Information Flow Tracking, SoC, Zynq, Zynq SoC, CoreSight, ARM Debug components, IFT, Dynamic information flow tracking, DIFT, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.6: Security and Protection, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

    Geographisches Schlagwort: Ghent, Belgium

    Verfügbarkeit: https://hal.science/hal-01558473
    https://hal.science/hal-01558473v1/document
    https://hal.science/hal-01558473v1/file/bare_conf.pdf
    https://doi.org/10.23919/fpl.2017.8056767

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  9. 9

    A semiempirical model for wakeup time estimation in power-gated logic clusters

    Autoren: Tovinakere Dwarakanath, Vivek Sentieys, Olivier Derrien, Steven et al.

    Weitere Verfasser: Tovinakere Dwarakanath, Vivek Sentieys, Olivier Derrien, Steven et al.

    Quelle: The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012 ; https://inria.hal.science/hal-00752606 ; The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012, Jun 2012, San Fransisco, United States. pp.48-55

    Schlagwörter: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.7: VLSI (very large scale integration), ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Geographisches Schlagwort: San Fransisco, United States

    Verfügbarkeit: https://inria.hal.science/hal-00752606

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  10. 10

    Accelerated and Highly Correlated ASIC Synthesis of AI Hardware Subsystems Using CGP.

    Autoren: Prashanth, H. C. Rao, Madhav

    Quelle: IET Computers & Digital Techniques (Wiley-Blackwell); 1/29/2024, Vol. 2024, p1-23, 23p

    Schlagwörter: LOGIC circuits, ARTIFICIAL intelligence, HARDWARE

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  11. 11

    RISC-V design using Free Open Source Software

    Autoren: Chaput, Jean-Paul Louërat, Marie-Minerve Chotin-Avot, Roselyne et al.

    Weitere Verfasser: Chaput, Jean-Paul Louërat, Marie-Minerve Chotin-Avot, Roselyne et al.

    Quelle: the RISC-V Week ; https://hal.sorbonne-universite.fr/hal-02316711 ; the RISC-V Week, Oct 2019, Paris, France

    Schlagwörter: ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.2: Design Aids, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.2: Design Aids, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.5: Microprocessors and microcomputers, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.2: Design Aids/B.7.2.2: Placement and routing, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [SPI.TRON]Engineering Sciences [physics]/Electronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics

    Geographisches Schlagwort: Paris, France

    Verfügbarkeit: https://hal.sorbonne-universite.fr/hal-02316711

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  12. 12

    N2S3, an Open-Source Scalable Spiking Neuromorphic Hardware Simulator

    Autoren: Boulet, Pierre Devienne, Philippe Falez, Pierre et al.

    Weitere Verfasser: Boulet, Pierre Devienne, Philippe Falez, Pierre et al.

    Quelle: https://hal.science/hal-01432133 ; [Research Report] Université de Lille 1, Sciences et Technologies; CRIStAL UMR 9189. 2017.

    Schlagwörter: simulation, neuromorphic architecture, SNN, SPiking neural networks, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.3: Simulation, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.7: Neural nets, [INFO.INFO-NE]Computer Science [cs]/Neural and Evolutionary Computing [cs.NE], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ET]Computer Science [cs]/Emerging Technologies [cs.ET], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

    Verfügbarkeit: https://hal.science/hal-01432133
    https://hal.science/hal-01432133v2/document
    https://hal.science/hal-01432133v2/file/n2s3.pdf

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  13. 13

    Analysis of Energy-Delay-Product for a 3D Vertical Nanowire FET Technology for Logic Applications

    Autoren: O'Connor, Ian Stanojevic, Zlatan Baumgartner, Oskar et al.

    Weitere Verfasser: O'Connor, Ian Stanojevic, Zlatan Baumgartner, Oskar et al.

    Quelle: https://hal.science/hal-02732902 ; 2020.

    Schlagwörter: ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics

    Verfügbarkeit: https://hal.science/hal-02732902
    https://hal.science/hal-02732902v1/document
    https://hal.science/hal-02732902v1/file/LEGO4TALK_EDP_Calculations.pdf

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  14. 14

    Soft timing closure for soft programmable logic cores: The ARGen approach

    Autoren: Bollengier, Théotime Lagadec, Loïc Najem, Mohamad et al.

    Weitere Verfasser: Bollengier, Théotime Lagadec, Loïc Najem, Mohamad et al.

    Quelle: ARC 2017 - 13th International Symposium on Applied Reconfigurable Computing ; https://hal.science/hal-01475251 ; ARC 2017 - 13th International Symposium on Applied Reconfigurable Computing, Delft University of Technology Apr 2017, Delft, Netherlands ; http://www.arc2017.tudelft.nl

    Schlagwörter: Reconfigurable cores, ACM: B.: Hardware, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.1: Design, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.2: Gate arrays, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.7: VLSI (very large scale integration), ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.11: Software Architectures/D.2.11.4: Patterns (e.g., client/server, pipeline, blackboard), [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Geographisches Schlagwort: Delft, Netherlands

    Verfügbarkeit: https://hal.science/hal-01475251
    https://hal.science/hal-01475251v1/document
    https://hal.science/hal-01475251v1/file/paper_6-4.pdf

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  15. 15

    From filters to transistors A library of analog schematic with automated sizing Team: FOSS EDA for analog and mixed circuit design

    Autoren: Porte, Jacky Louërat, Marie-Minerve Circuits Intégrés Numériques et Analogiques (CIAN) et al.

    Weitere Verfasser: Porte, Jacky Louërat, Marie-Minerve Circuits Intégrés Numériques et Analogiques (CIAN) et al.

    Quelle: Free Silicon Conference ; https://hal.sorbonne-universite.fr/hal-02316744 ; Free Silicon Conference, LIP6, Mar 2019, Paris, France

    Schlagwörter: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.2: Design Aids, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [SPI.TRON]Engineering Sciences [physics]/Electronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics

    Geographisches Schlagwort: Paris, France

    Verfügbarkeit: https://hal.sorbonne-universite.fr/hal-02316744

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  16. 16

    Digital Systems Design

    Autoren: Sameni, Reza Shiraz University (Shiraz University)

    Weitere Verfasser: Sameni, Reza Shiraz University (Shiraz University)

    Quelle: https://hal.science/cel-01815308 ; Engineering school. Iran. 2018.

    Schlagwörter: ACM: C.: Computer Systems Organization, ACM: B.: Hardware, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.1: Design, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-LO]Computer Science [cs]/Logic in Computer Science [cs.LO]

    Verfügbarkeit: https://hal.science/cel-01815308
    https://hal.science/cel-01815308v1/document
    https://hal.science/cel-01815308v1/file/CourseSlides2018.pdf

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  17. 17

    IPT-EGVE Symposium (2007) B. Fröhlich, R. Blach, and R. van Liere (Editors) Widget Manipulation Revisited: a Case Study in Modeling Interactions Between Experimental Conditions

    Weitere Verfasser: The Pennsylvania State University CiteSeerX Archives

    Quelle: http://www.cwi.nl/~robertl/papers/2007/egve2/paper.pdf.

    Schlagwörter: Widgets, interaction, virtual environments. Categories and Subject Descriptors (according to ACM CCS, B.8.2 [Hardware, Performance and ReliabilityPerformance Analysis and Design Aids, B.4.2 [Hardware, Input/Output and Data CommunicationsInput/Output

    Dateibeschreibung: application/pdf

    Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.63.4912; http://www.cwi.nl/~robertl/papers/2007/egve2/paper.pdf

    Verfügbarkeit: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.63.4912
    http://www.cwi.nl/~robertl/papers/2007/egve2/paper.pdf

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  18. 18

    Throughput and FIFO Sizing: an Application to Latency-Insensitive Design

    Autoren: Boucaron, Julien Coadou, Anthony de Simone, Robert et al.

    Weitere Verfasser: Boucaron, Julien Coadou, Anthony de Simone, Robert et al.

    Quelle: https://inria.hal.science/inria-00381644 ; [Research Report] RR-6919, INRIA. 2009, pp.19.

    Schlagwörter: FIFO sizing, Buffer sizing, Throughput, Latency-Insensitive Design, Marked Graphs, ACM: F.: Theory of Computation/F.1: COMPUTATION BY ABSTRACT DEVICES/F.1.1: Models of Computation, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS, [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Verfügbarkeit: https://inria.hal.science/inria-00381644
    https://inria.hal.science/inria-00381644v1/document
    https://inria.hal.science/inria-00381644v1/file/RR-6919.pdf

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  19. 19

    Contributions to Program Optimization and High-Level Synthesis ; Contributions à l'optimisation de programmes et à la synthèse de circuits haut-niveau

    Autoren: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Centre Inria de l'Université Grenoble Alpes et al.

    Weitere Verfasser: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Centre Inria de l'Université Grenoble Alpes et al.

    Quelle: https://inria.hal.science/tel-02151877 ; Hardware Architecture [cs.AR]. ENS de Lyon, 2019.

    Schlagwörter: High-Level Synthesis, Compilation Techniques, Automatic Parallelization, Compilation, Parallélisation automatique, Synthèse haut-niveau, FPGA, ACM: B.: Hardware, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL]

    Verfügbarkeit: https://inria.hal.science/tel-02151877
    https://inria.hal.science/tel-02151877v2/document
    https://inria.hal.science/tel-02151877v2/file/hdr-alias.pdf

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  20. 20

    High-Level Synthesis of Pipelined FSM from Loop Nests

    Autoren: Alias, Christophe Rastello, Fabrice Plesco, Alexandru et al.

    Weitere Verfasser: Alias, Christophe Rastello, Fabrice Plesco, Alexandru et al.

    Quelle: https://inria.hal.science/hal-01301334 ; [Research Report] 8900, INRIA. 2016, pp.18.

    Schlagwörter: High-level synthesis, fine-grain loop optimization, control automaton, pipeline, ACM: B.: Hardware/B.1: CONTROL STRUCTURES AND MICROPROGRAMMING, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.2: Design Aids, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.6: Optimization, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

    Relation: Report N°: 8900

    Verfügbarkeit: https://inria.hal.science/hal-01301334
    https://inria.hal.science/hal-01301334v2/document
    https://inria.hal.science/hal-01301334v2/file/RR-8900.pdf

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