Výsledky vyhledávání - ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization

A Polynomial Based Approach to Wakeup Time and Energy Estimation in Power-Gated Logic Clusters

Autoři: D. Tovinakere, Vivek Sentieys, Olivier Derrien, Steven a další

Přispěvatelé: D. Tovinakere, Vivek Sentieys, Olivier Derrien, Steven a další

Zdroj: ISSN: 1546-1998 ; Journal of Low Power Electronics ; https://inria.hal.science/hal-00747721 ; Journal of Low Power Electronics, 2011, 7 (4), pp.482-489. ⟨10.1166/jolpe.2011.1159⟩.

Témata: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.2: Design Aids, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Dostupnost: https://inria.hal.science/hal-00747721
https://doi.org/10.1166/jolpe.2011.1159

Formal Methods for Schedulings of Latency-Insensitive Designs

Autoři: Boucaron, Julien Millo, Jean-Vivien de Simone, Robert a další

Přispěvatelé: Boucaron, Julien Millo, Jean-Vivien de Simone, Robert a další

Zdroj: https://inria.hal.science/inria-00137495 ; [Research Report] RR-6149, INRIA. 2007, pp.25.

Témata: repetitive cyclic scheduling, formal models, synchronous languages, digital circuits, latency insensitive designs, Systems-on-chip, electronic system-level design, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids, ACM: C.: Computer Systems Organization/C.4: PERFORMANCE OF SYSTEMS, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.2: Design Aids, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation, [INFO.INFO-RO]Computer Science [cs]/Operations Research [math.OC], [INFO.INFO-SC]Computer Science [cs]/Symbolic Computation [cs.SC]

Dostupnost: https://inria.hal.science/inria-00137495
https://inria.hal.science/inria-00137495v2/document
https://inria.hal.science/inria-00137495v2/file/RR-6149.pdf

Model Driven Engineering Benefits for High Level Synthesis

Autoři: Le Beux, Sébastien Marquet, Philippe Dekeyser, Jean-Luc a další

Přispěvatelé: Le Beux, Sébastien Marquet, Philippe Dekeyser, Jean-Luc a další

Zdroj: https://inria.hal.science/inria-00311300 ; [Research Report] RR-6615, INRIA. 2008, pp.46.

Témata: ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.1: Design Styles/B.6.1.5: Parallel circuits, ACM: B.: Hardware/B.8: PERFORMANCE AND RELIABILITY/B.8.2: Performance Analysis and Design Aids, ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.5: Model Development/I.6.5.0: Modeling methodologies, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS/C.3.2: Real-time and embedded systems, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Dostupnost: https://inria.hal.science/inria-00311300
https://inria.hal.science/inria-00311300/document
https://inria.hal.science/inria-00311300/file/RR-6615.pdf

Contributions to Program Optimization and High-Level Synthesis ; Contributions à l'optimisation de programmes et à la synthèse de circuits haut-niveau

Autoři: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Centre Inria de l'Université Grenoble Alpes a další

Přispěvatelé: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Centre Inria de l'Université Grenoble Alpes a další

Zdroj: https://inria.hal.science/tel-02151877 ; Hardware Architecture [cs.AR]. ENS de Lyon, 2019.

Témata: High-Level Synthesis, Compilation Techniques, Automatic Parallelization, Compilation, Parallélisation automatique, Synthèse haut-niveau, FPGA, ACM: B.: Hardware, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL]

Dostupnost: https://inria.hal.science/tel-02151877
https://inria.hal.science/tel-02151877v2/document
https://inria.hal.science/tel-02151877v2/file/hdr-alias.pdf

FPGA-Specific Synthesis of Loop-Nests with Pipelined Computational Cores

Autoři: Alias, Christophe Pasca, Bogdan Plesco, Alexandru a další

Přispěvatelé: Alias, Christophe Pasca, Bogdan Plesco, Alexandru a další

Zdroj: https://inria.hal.science/inria-00606977 ; [Research Report] RR-7674, INRIA. 2011, pp.33.

Témata: High-Level Synthesis, Compiler, ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES/B.2.4: High-Speed Arithmetic, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS/C.3.3: Signal processing systems, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL], [INFO.INFO-IA]Computer Science [cs]/Computer Aided Engineering, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Dostupnost: https://inria.hal.science/inria-00606977
https://inria.hal.science/inria-00606977v1/document
https://inria.hal.science/inria-00606977v1/file/RR-7674.pdf

A semiempirical model for wakeup time estimation in power-gated logic clusters

Autoři: Tovinakere Dwarakanath, Vivek Sentieys, Olivier Derrien, Steven a další

Přispěvatelé: Tovinakere Dwarakanath, Vivek Sentieys, Olivier Derrien, Steven a další

Zdroj: The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012 ; https://inria.hal.science/hal-00752606 ; The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012, Jun 2012, San Fransisco, United States. pp.48-55

Témata: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.7: VLSI (very large scale integration), ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Geografické téma: San Fransisco, United States

Dostupnost: https://inria.hal.science/hal-00752606

Smart Vision Chip for colon exploration ; Smart Vision Chip pour l’exploration du colon

Autoři: Chuquimia, Orlando Systèmes Electroniques (SYEL) LIP6 a další

Přispěvatelé: Chuquimia, Orlando Systèmes Electroniques (SYEL) LIP6 a další

Zdroj: https://tel.archives-ouvertes.fr/tel-02494557 ; Imagerie médicale. Sorbonne Université, 2019. Français.

Témata: Automatic polyp detection, intelligent endoscopic capsule, Hough transform, fuzzy trees, fuzzy forest, artificial vision and hardware accelerator, vision artificielle et accélérateur matériel, Détection automatique des polypes, capsule endoscopique intelligente, transformée d’Hough, arbres flous, forets floues, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: C.: Computer Systems Organization/C.5: COMPUTER SYSTEM IMPLEMENTATION, ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE/I.2.6: Learning, ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE/I.2.9: Robotics, ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE/I.2.10: Vision and Scene Understanding, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.7: Feature Measurement/I.4.7.5: Texture, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.0: General/I.4.0.1: Image processing software, [INFO.INFO-IM]Computer Science [cs]/Medical Imaging, [INFO.INFO-CV]Computer Science [cs]/Computer Vision and Pattern Recognition [cs.CV], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI], [INFO.INFO-RB]Computer Science [cs]/Robotics [cs.RO]

Relation: tel-02494557; https://tel.archives-ouvertes.fr/tel-02494557; https://tel.archives-ouvertes.fr/tel-02494557/document; https://tel.archives-ouvertes.fr/tel-02494557/file/thhese_archivage__N%C2%B0dossier.pdf

Dostupnost: https://tel.archives-ouvertes.fr/tel-02494557
https://tel.archives-ouvertes.fr/tel-02494557/document
https://tel.archives-ouvertes.fr/tel-02494557/file/thhese_archivage__N%C2%B0dossier.pdf

Dynamic Profiling and Fuzzy-Logic-Based Optimization of Sensor Network Platforms.

Autoři: LIZARRAGA, ADRIAN LYSECKY, ROMAN LYSECKY, SUSAN a další

Zdroj: ACM Transactions on Embedded Computing Systems; Dec2013, Vol. 13 Issue 3, p51:1-51:29, 29p

Témata: DYNAMICAL systems, FUZZY logic, MATHEMATICAL optimization, SENSOR networks, APPLICATION software, COMPUTER engineering

High-Level Synthesis of Pipelined FSM from Loop Nests

Autoři: Alias, Christophe Rastello, Fabrice Plesco, Alexandru a další

Přispěvatelé: Alias, Christophe Rastello, Fabrice Plesco, Alexandru a další

Zdroj: https://inria.hal.science/hal-01301334 ; [Research Report] 8900, INRIA. 2016, pp.18.

Témata: High-level synthesis, fine-grain loop optimization, control automaton, pipeline, ACM: B.: Hardware/B.1: CONTROL STRUCTURES AND MICROPROGRAMMING, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.2: Design Aids, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.6: Optimization, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

Relation: Report N°: 8900

Dostupnost: https://inria.hal.science/hal-01301334
https://inria.hal.science/hal-01301334v2/document
https://inria.hal.science/hal-01301334v2/file/RR-8900.pdf

Toward Understanding FPGA Synthesis Tool Bugs.

Autoři: Zhang, Yi Jiang, He Guo, Shikai a další

Zdroj: ACM Transactions on Software Engineering & Methodology; Sep2025, Vol. 34 Issue 7, p1-37, 37p

Témata: FIELD programmable gate arrays, RELIABILITY in engineering, SOFTWARE validation, EMPIRICAL research, MATHEMATICAL optimization, SOFTWARE development tools

Accelerated and Highly Correlated ASIC Synthesis of AI Hardware Subsystems Using CGP.

Autoři: Prashanth, H. C. Rao, Madhav

Zdroj: IET Computers & Digital Techniques (Wiley-Blackwell); 1/29/2024, Vol. 2024, p1-23, 23p

Témata: LOGIC circuits, ARTIFICIAL intelligence, HARDWARE

SHIFT: Selective Hardware Information Flow Tracking Driven by Deterministic Constraints.

Autoři: Sun, Haodong Yang, Zhi Jin, Shuyuan a další

Zdroj: ACM Journal on Emerging Technologies in Computing Systems; Oct2025, Vol. 21 Issue 4, p1-16, 16p

Témata: HARDWARE design & construction, CONSTRAINED optimization, MATHEMATICAL optimization, SCIENTIFIC apparatus & instruments, RISK assessment

A Comparative Study of the Precision of Stack Cache Occupancy Analyses

Autoři: Naji, Amine Brandner, Florian Unité d'Informatique et d'Ingénierie des Systèmes (U2IS) a další

Přispěvatelé: Naji, Amine Brandner, Florian Unité d'Informatique et d'Ingénierie des Systèmes (U2IS) a další

Zdroj: 9th Junior Researcher Workshop on Real-Time Computing
https://hal.science/hal-01246343
9th Junior Researcher Workshop on Real-Time Computing, Julien Forget, Nov 2015, Lille, France. pp.4
http://rtns2015.lifl.fr/jrwrtc2015/

Témata: Real-Time Systems, Stack Cache, Program Analysis, ACM: F.: Theory of Computation/F.3: LOGICS AND MEANINGS OF PROGRAMS/F.3.2: Semantics of Programming Languages, ACM: B.: Hardware/B.3: MEMORY STRUCTURES/B.3.3: Performance Analysis and Design Aids, [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Geografické téma: Lille, France

Dostupnost: https://hal.science/hal-01246343

Throughput and FIFO Sizing: an Application to Latency-Insensitive Design

Autoři: Boucaron, Julien Coadou, Anthony de Simone, Robert a další

Přispěvatelé: Boucaron, Julien Coadou, Anthony de Simone, Robert a další

Zdroj: https://inria.hal.science/inria-00381644 ; [Research Report] RR-6919, INRIA. 2009, pp.19.

Témata: FIFO sizing, Buffer sizing, Throughput, Latency-Insensitive Design, Marked Graphs, ACM: F.: Theory of Computation/F.1: COMPUTATION BY ABSTRACT DEVICES/F.1.1: Models of Computation, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS, [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Dostupnost: https://inria.hal.science/inria-00381644
https://inria.hal.science/inria-00381644v1/document
https://inria.hal.science/inria-00381644v1/file/RR-6919.pdf

A Hybrid Nano/CMOS Dynamically Reconfigurable System-Part II: Design Optimization Flow.

Autoři: Wei Zhang Jha, Niraj K. Li Shang

Zdroj: ACM Journal on Emerging Technologies in Computing Systems; 2009, Vol. 5 Issue 3, p13.1-13:31, 31p, 11 Diagrams, 7 Charts, 1 Graph

Témata: COMPLEMENTARY metal oxide semiconductors, COMPUTER storage devices, ADAPTIVE computing systems, DIGITAL electronics, MICROPROCESSORS, PROGRAMMABLE logic devices, ENGINEERING design

HARDWARE AIDS FOR AUTOMATA DESIGN

Autoři: Reilly, Norman B RAND CORP SANTA MONICA CA

Přispěvatelé: Reilly, Norman B RAND CORP SANTA MONICA CA

Zdroj: DTIC AND NTIS

Témata: Computer Hardware, Bionics, BIONICS, AUTOMATA, CIRCUITS, COMPUTER LOGIC, COMPUTERS, CONTROL SYSTEMS, MATHEMATICAL MODELS, NERVE CELLS, NERVOUS SYSTEM

Popis souboru: text/html

Relation: http://www.dtic.mil/docs/citations/AD0646393

Dostupnost: http://www.dtic.mil/docs/citations/AD0646393
http://oai.dtic.mil/oai/oai?&verb=getRecord&metadataPrefix=html&identifier=AD0646393

Symbolic noise analysis approach to computational hardware optimization

Autoři: Arash Ahmadi Mark Zwolinski The Pennsylvania State University CiteSeerX Archives

Přispěvatelé: Arash Ahmadi Mark Zwolinski The Pennsylvania State University CiteSeerX Archives

Zdroj: http://eprints.soton.ac.uk/265306/1/Symbolic_Noise_Analysis_Approach_to_Computational_Hardware_Optimization.pdf.

Témata: B.2 [Arithmetic and Logic Structures, Performance Analysis and Design Aids General Terms Algorithms, Design Keywords Computational error, word-length optimization, high level synthesis, computer

Popis souboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.580.3215; http://eprints.soton.ac.uk/265306/1/Symbolic_Noise_Analysis_Approach_to_Computational_Hardware_Optimization.pdf

Dostupnost: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.580.3215
http://eprints.soton.ac.uk/265306/1/Symbolic_Noise_Analysis_Approach_to_Computational_Hardware_Optimization.pdf

GUSTO: An Automatic Generation and Optimization Tool for Matrix Inversion Architectures.

Autoři: IRTURK, ALI BENSON, BRIDGET MIRZAEI, SHAHNAM a další

Zdroj: ACM Transactions on Embedded Computing Systems; Mar2010, Vol. 9 Issue 4, p32-32:21, 21p, 9 Diagrams, 2 Charts, 10 Graphs

Témata: MATRIX inversion, FIELD programmable gate arrays, SYSTEMS design, GENERALIZED inverses of linear operators, PROGRAMMABLE logic devices

Using Reconfigurability to Achieve RealTime Profiling for Hardware/Software Codesign

Autoři: Lesley Shannon Paul Chow The Pennsylvania State University CiteSeerX Archives

Přispěvatelé: Lesley Shannon Paul Chow The Pennsylvania State University CiteSeerX Archives

Zdroj: http://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/2004/fpga04/pdffiles/p190.pdf.

Témata: Categories and Subject Descriptors B.6.3 [Logic Design, Design Aids—optimization, C.4 [Computer Systems Organization, Performance of Systems—Measurement Techniques General Terms Design, Measurement, Performance Keywords FPGA, embedded processor, hardware/software codesign, performance measurement

Popis souboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.580.9960

Dostupnost: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.580.9960
http://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/2004/fpga04/pdffiles/p190.pdf

Integrated Worst-Case Execution Time Estimation of Multicore Applications

Autoři: Potop-Butucaru, Dumitru Puaut, Isabelle Models and methods of analysis and optimization for systems with real-time and embedding constraints (AOSTE) a další

Přispěvatelé: Potop-Butucaru, Dumitru Puaut, Isabelle Models and methods of analysis and optimization for systems with real-time and embedding constraints (AOSTE) a další

Zdroj: 13th International Workshop on Worst-Case Execution Time Analysis
https://inria.hal.science/hal-00909330
13th International Workshop on Worst-Case Execution Time Analysis, Jul 2013, Paris, France. pp.21-31, ⟨10.4230/OASIcs.WCET.2013.i⟩

Témata: WCET estimation, multicore architecture, parallel programming, ACM: B.: Hardware/B.8: PERFORMANCE AND RELIABILITY/B.8.2: Performance Analysis and Design Aids, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS, ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.4: Software/Program Verification, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Geografické téma: Paris, France

Dostupnost: https://inria.hal.science/hal-00909330
https://doi.org/10.4230/OASIcs.WCET.2013.i