Výsledky vyhľadávania - ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis

Model Driven Engineering Benefits for High Level Synthesis

Autori: Le Beux, Sébastien Marquet, Philippe Dekeyser, Jean-Luc a ďalší

Prispievatelia: Le Beux, Sébastien Marquet, Philippe Dekeyser, Jean-Luc a ďalší

Zdroj: https://inria.hal.science/inria-00311300 ; [Research Report] RR-6615, INRIA. 2008, pp.46.

Predmety: ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.1: Design Styles/B.6.1.5: Parallel circuits, ACM: B.: Hardware/B.8: PERFORMANCE AND RELIABILITY/B.8.2: Performance Analysis and Design Aids, ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.5: Model Development/I.6.5.0: Modeling methodologies, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS/C.3.2: Real-time and embedded systems, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Dostupnosť: https://inria.hal.science/inria-00311300
https://inria.hal.science/inria-00311300/document
https://inria.hal.science/inria-00311300/file/RR-6615.pdf

FPGA-Specific Synthesis of Loop-Nests with Pipelined Computational Cores

Autori: Alias, Christophe Pasca, Bogdan Plesco, Alexandru a ďalší

Prispievatelia: Alias, Christophe Pasca, Bogdan Plesco, Alexandru a ďalší

Zdroj: https://inria.hal.science/inria-00606977 ; [Research Report] RR-7674, INRIA. 2011, pp.33.

Predmety: High-Level Synthesis, Compiler, ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES/B.2.4: High-Speed Arithmetic, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS/C.3.3: Signal processing systems, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL], [INFO.INFO-IA]Computer Science [cs]/Computer Aided Engineering, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Dostupnosť: https://inria.hal.science/inria-00606977
https://inria.hal.science/inria-00606977v1/document
https://inria.hal.science/inria-00606977v1/file/RR-7674.pdf

Smart Vision Chip for colon exploration ; Smart Vision Chip pour l’exploration du colon

Autori: Chuquimia, Orlando Systèmes Electroniques (SYEL) LIP6 a ďalší

Prispievatelia: Chuquimia, Orlando Systèmes Electroniques (SYEL) LIP6 a ďalší

Zdroj: https://tel.archives-ouvertes.fr/tel-02494557 ; Imagerie médicale. Sorbonne Université, 2019. Français.

Predmety: Automatic polyp detection, intelligent endoscopic capsule, Hough transform, fuzzy trees, fuzzy forest, artificial vision and hardware accelerator, vision artificielle et accélérateur matériel, Détection automatique des polypes, capsule endoscopique intelligente, transformée d’Hough, arbres flous, forets floues, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: C.: Computer Systems Organization/C.5: COMPUTER SYSTEM IMPLEMENTATION, ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE/I.2.6: Learning, ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE/I.2.9: Robotics, ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE/I.2.10: Vision and Scene Understanding, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.7: Feature Measurement/I.4.7.5: Texture, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.0: General/I.4.0.1: Image processing software, [INFO.INFO-IM]Computer Science [cs]/Medical Imaging, [INFO.INFO-CV]Computer Science [cs]/Computer Vision and Pattern Recognition [cs.CV], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI], [INFO.INFO-RB]Computer Science [cs]/Robotics [cs.RO]

Relation: tel-02494557; https://tel.archives-ouvertes.fr/tel-02494557; https://tel.archives-ouvertes.fr/tel-02494557/document; https://tel.archives-ouvertes.fr/tel-02494557/file/thhese_archivage__N%C2%B0dossier.pdf

Dostupnosť: https://tel.archives-ouvertes.fr/tel-02494557
https://tel.archives-ouvertes.fr/tel-02494557/document
https://tel.archives-ouvertes.fr/tel-02494557/file/thhese_archivage__N%C2%B0dossier.pdf

Contributions to Program Optimization and High-Level Synthesis ; Contributions à l'optimisation de programmes et à la synthèse de circuits haut-niveau

Autori: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Centre Inria de l'Université Grenoble Alpes a ďalší

Prispievatelia: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Centre Inria de l'Université Grenoble Alpes a ďalší

Zdroj: https://inria.hal.science/tel-02151877 ; Hardware Architecture [cs.AR]. ENS de Lyon, 2019.

Predmety: High-Level Synthesis, Compilation Techniques, Automatic Parallelization, Compilation, Parallélisation automatique, Synthèse haut-niveau, FPGA, ACM: B.: Hardware, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL]

Dostupnosť: https://inria.hal.science/tel-02151877
https://inria.hal.science/tel-02151877v2/document
https://inria.hal.science/tel-02151877v2/file/hdr-alias.pdf

Time-redundancy transformations for adaptive fault-tolerant circuits

Autori: Burlyaev, Dmitry Fradet, Pascal Girault, Alain a ďalší

Prispievatelia: Burlyaev, Dmitry Fradet, Pascal Girault, Alain a ďalší

Zdroj: 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)
https://inria.hal.science/hal-01253111
2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Jun 2015, Montreal, Canada. ⟨10.1109/AHS.2015.7231164⟩

Predmety: digital circuits, fault tolerance, time redundancy, circuit transformation, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.3: Reliability and Testing/B.5.3.2: Redundant design, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.2: Design Aids/B.5.2.0: Automatic synthesis, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-PF]Computer Science [cs]/Performance [cs.PF]

Geografické téma: Montreal

Time: Montreal, Canada

Dostupnosť: https://inria.hal.science/hal-01253111
https://doi.org/10.1109/AHS.2015.7231164

A new canonical form for fast Boolean matching in logic synthesis and verification

Autori: Afshin Abdollahi Massoud Pedram The Pennsylvania State University CiteSeerX Archives

Prispievatelia: Afshin Abdollahi Massoud Pedram The Pennsylvania State University CiteSeerX Archives

Zdroj: http://atrak.usc.edu/~afshin/DAC05B.pdf.

Predmety: Categories &, Subject Descriptors B.6.3 [Hardware] Logic Design, Design aids − Automatic synthesis, Optimization, verification. General Terms Algorithms, Design, Verification

Popis súboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.603.1939; http://atrak.usc.edu/~afshin/DAC05B.pdf

Dostupnosť: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.603.1939
http://atrak.usc.edu/~afshin/DAC05B.pdf

Automated Synthesis of Digital Hardware.

Autori: Hafer Parker

Zdroj: IEEE Transactions on Computers; 1982, Vol. C-31 Issue 2, p93-109, 17p

Evaluating Large Language Models for Automatic Register Transfer Logic Generation for Combinational Circuits via High-Level Synthesis.

Autori: Swaroopa, Sneha Mukherjee, Rijoy Debnath, Anushka a ďalší

Zdroj: Foundations & Trends in Electronic Design Automation; 2024, Vol. 14 Issue 4, p315-337, 23p

Predmety: LANGUAGE models, COMBINATIONAL circuits, INTEGRATED circuit verification, C++, GRAPES

The automatic synthesis of digital systems.

Autori: Thomas, D.E.

Zdroj: Proceedings of the IEEE; 1981, Vol. 69 Issue 10, p1200-1211, 12p

Techniques for the Synthesis of Reversible Toffoli Networks

Autori: D. Maslov G. W. Dueck D. M. Miller a ďalší

Prispievatelia: D. Maslov G. W. Dueck D. M. Miller a ďalší

Zdroj: http://www.cs.uvic.ca/~mmiller/publications/a42-maslov.pdf.

Predmety: B.6[Logic Design] [B.6.1 Design Styles, B.6.3 Design Aids, Computer-aided design (CAD, Automatic synthesis, Optimization, Switching theory General Terms, Hardware, Theory of Computation Additional Key Words and Phrases, quantum computing, reversible logic synthesis, circuit optimization 42

Popis súboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.216.9857

Dostupnosť: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.216.9857
http://www.cs.uvic.ca/~mmiller/publications/a42-maslov.pdf

A Polynomial Based Approach to Wakeup Time and Energy Estimation in Power-Gated Logic Clusters

Autori: D. Tovinakere, Vivek Sentieys, Olivier Derrien, Steven a ďalší

Prispievatelia: D. Tovinakere, Vivek Sentieys, Olivier Derrien, Steven a ďalší

Zdroj: ISSN: 1546-1998 ; Journal of Low Power Electronics ; https://inria.hal.science/hal-00747721 ; Journal of Low Power Electronics, 2011, 7 (4), pp.482-489. ⟨10.1166/jolpe.2011.1159⟩.

Predmety: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.2: Design Aids, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Dostupnosť: https://inria.hal.science/hal-00747721
https://doi.org/10.1166/jolpe.2011.1159

Specification and Synthesis of Hardware Checkpointing and Rollback Mechanisms.

Autori: Carven Chan Schwartz-Narbonne, Daniel Sethi, Divjyot a ďalší

Zdroj: DAC: Annual ACM/IEEE Design Automation Conference; Jun2012, p1226-1232, 7p

Predmety: ROLLBACK recovery (Computer science), RTL (Computer program language), COMPUTER hardware description languages, NETWORK routers, INTEGRATED circuit interconnections, NETWORK performance, SYSTEMS design

Automatic Design of Area-Efficient Configurable ASIC Cores.

Autori: Compton, Katherine Hauck, Scott

Zdroj: IEEE Transactions on Computers; May2007, Vol. 56 Issue 5, p662-672, 11p, 2 Black and White Photographs, 8 Diagrams, 4 Charts, 1 Graph

Predmety: COMPUTER input-output equipment, COMPUTER software, STANDARD cells, LOGIC design, INTEGRATED circuits, PROGRAM transformation, ROUTING (Computer network management), HEURISTIC programming

Accelerated and Highly Correlated ASIC Synthesis of AI Hardware Subsystems Using CGP.

Autori: Prashanth, H. C. Rao, Madhav

Zdroj: IET Computers & Digital Techniques (Wiley-Blackwell); 1/29/2024, Vol. 2024, p1-23, 23p

Predmety: LOGIC circuits, ARTIFICIAL intelligence, HARDWARE

Are Logic Synthesis Tools Robust?

Autori: Puggelli, Alberto Welp, Tobias Kuehlmann, Andreas a ďalší

Zdroj: DAC: Annual ACM/IEEE Design Automation Conference; Jun2011, p633-638, 6p, 2 Diagrams, 4 Charts, 5 Graphs

Predmety: VERILOG (Computer hardware description language), ROBUST control, COMPUTER software correctness, ALGORITHMS, MATHEMATICAL transformations

Synchronous Digital Circuits as Functional Programs

Autori: Peter Gammie The Pennsylvania State University CiteSeerX Archives

Prispievatelia: Peter Gammie The Pennsylvania State University CiteSeerX Archives

Zdroj: http://www.nicta.com.au/pub?doc=6480.

Predmety: Categories and Subject Descriptors, A.1 [General Literature, Introductory and Survey, B.5.2 [Register-transfer-level Implementation, Design Aids—Automatic synthesis, Hardware Description Languages, B.6.3[Logic Design, B.7.2[Integrated Circuits, Design Aids—Layout, Simulation, Verification, D.3.2 [Software, Programming Languages—Applicative (functional) languages General Terms, Circuits, Design, Functional Programming

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.433.1977; http://www.nicta.com.au/pub?doc=6480

Dostupnosť: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.433.1977
http://www.nicta.com.au/pub?doc=6480

Cofactor Sharing for Reversible Logic Synthesis.

Autori: SHAFAEI, ALIREZA SAEEDI, MEHDI PEDRAM, MASSOUD

Zdroj: ACM Journal on Emerging Technologies in Computing Systems; Oct2014, Vol. 11 Issue 2, p14-14:21, 21p

Predmety: LOGIC circuit synthesis (Electronic design), ALGORITHMS, COMPUTER-aided design, SPARSE graphs, COMPUTER simulation

GUSTO: An Automatic Generation and Optimization Tool for Matrix Inversion Architectures.

Autori: IRTURK, ALI BENSON, BRIDGET MIRZAEI, SHAHNAM a ďalší

Zdroj: ACM Transactions on Embedded Computing Systems; Mar2010, Vol. 9 Issue 4, p32-32:21, 21p, 9 Diagrams, 2 Charts, 10 Graphs

Predmety: MATRIX inversion, FIELD programmable gate arrays, SYSTEMS design, GENERALIZED inverses of linear operators, PROGRAMMABLE logic devices

Optimal Clock Period FPGA Technology Mapping for Sequential Circuits

Autori: Peichen Pan C. L. Liu The Pennsylvania State University CiteSeerX Archives

Prispievatelia: Peichen Pan C. L. Liu The Pennsylvania State University CiteSeerX Archives

Zdroj: http://www.cs.ucla.edu/~mrivero/PAPER/p437-pan.pdf.

Predmety: Categories and Subject Descriptors, B.6.1 [Hardware, Design Styles—sequential circuits, B.6.3 [Hardware, Design Aids—automatic synthesis, optimization General Terms, algorithms, performance Additional Key Words and Phrases, Clock period, field–programmable gate arrays, FPGAs, logic replication, look–up tables, retiming, sequential synthesis, technology mapping

Popis súboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.3.7958

Dostupnosť: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.3.7958
http://www.cs.ucla.edu/~mrivero/PAPER/p437-pan.pdf

Data Reorganization Engines for the Next Generation of System-On-a-Chip FPGAs*

Autori: Pedro C. Diniz Joonseok Park The Pennsylvania State University CiteSeerX Archives

Prispievatelia: Pedro C. Diniz Joonseok Park The Pennsylvania State University CiteSeerX Archives

Zdroj: http://www.sigda.org/Archives/ProceedingArchives/Fpga/Fpga2002/papers/2002/fpga02/pdffiles/8_3.pdf.

Predmety: Categories and Subject Descriptors B.5.1 [Register-Transfer-Level Implementation, Design Aids – automatic synthesis, B.7.1 [Integrated Circuits, Types and Design Styles – algorithm implementation in hardware, B.6.2 [Logic Design, Design Styles – memory control and access, D.3.4 [Programming Languages, Processors – compilers. Keywords Data Reorganization, High-level Synthesis, Field-Programmable- Gate-Arrays (FPGAs

Popis súboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.108.1615; http://www.sigda.org/Archives/ProceedingArchives/Fpga/Fpga2002/papers/2002/fpga02/pdffiles/8_3.pdf

Dostupnosť: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.108.1615
http://www.sigda.org/Archives/ProceedingArchives/Fpga/Fpga2002/papers/2002/fpga02/pdffiles/8_3.pdf