Search Results - ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.1: Design Styles/B.6.1.5: Parallel circuits

Particle graphics on reconfigurable hardware

Authors: John S. Beeckler Warren J. Gross The Pennsylvania State University CiteSeerX Archives

Contributors: John S. Beeckler Warren J. Gross The Pennsylvania State University CiteSeerX Archives

Source: http://www.iml.ece.mcgill.ca/~wjgross/papers/Beeckler_Gross_TRETS_2008.pdf.

Subject Terms: Categories and Subject Descriptors, B.6.1 [Logic Design, Design Styles—Parallel circuits, B.7.1 [Integrated Circuits, Types and Design Styles—Algorithms implemented in hardware, gate arrays General Terms, Algorithms, Design, Performance Additional Key Words and Phrases, Reconfigurable computing, FPGAs, particle systems, special- purpose architectures ACM Reference Format

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Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.487.6675; http://www.iml.ece.mcgill.ca/~wjgross/papers/Beeckler_Gross_TRETS_2008.pdf

Availability: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.487.6675
http://www.iml.ece.mcgill.ca/~wjgross/papers/Beeckler_Gross_TRETS_2008.pdf

Incremental SAT-Based Reverse Engineering of Camouflaged Logic Circuits.

Authors: Yu, Cunxi Zhang, Xiangyu Liu, Duo et al.

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Oct2017, Vol. 36 Issue 10, p1647-1659, 13p

Subject Terms: LOGIC circuits, REVERSE engineering, COMBINATIONAL circuits, ALGORITHMS, INTEGRATED circuit design

AdaTest: Reinforcement Learning and Adaptive Sampling for On-chip Hardware Trojan Detection.

Authors: HUILI CHEN XINQIAO ZHANG KE HUANG et al.

Source: ACM Transactions on Embedded Computing Systems; Mar2023, Vol. 22 Issue 2, p1-23, 23p

Subject Terms: REINFORCEMENT learning, REWARD (Psychology), ADAPTIVE testing, INTEGRATED circuits, SOFTWARE architecture, HARDWARE

Performance-Driven Clustering of Asynchronous Circuits.

Authors: Dimou, Georgios D. Beerel, Peter A. Lines, Andrew M.

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Feb2014, Vol. 33 Issue 2, p197-209, 13p

Subject Terms: ASYNCHRONOUS circuits, DIGITAL electronics, ELECTRONIC circuits, COMPUTER hardware description languages, METHODOLOGY

Design of Reversible Sequential Circuits Optimizing Quantum Cost, Delay, and Garbage Outputs.

Authors: Thapliyal, Himanshu Ranganathan, Nagarajan

Source: ACM Journal on Emerging Technologies in Computing Systems; 2010, Vol. 6 Issue 4, p14:1-14:31, 31p, 24 Diagrams, 10 Charts, 1 Graph

Subject Terms: LOGIC circuits, SEQUENTIAL circuits, MATHEMATICAL optimization, INFORMATION processing, QUANTUM dots, CELLULAR automata, COMPUTATIONAL complexity

Delay Insensitive Ternary CMOS Logic for Secure Hardware.

Authors: Nair, Ravi S. P. Smith, Scott C. Jia Di

Source: Journal of Low Power Electronics & Applications; 2015, Vol. 5 Issue 3, p183-215, 33p

Subject Terms: CMOS logic circuits, ASYNCHRONOUS circuits

Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction

Authors: Arash Saifhashemi Hossein Pedram The Pennsylvania State University CiteSeerX Archives

Contributors: Arash Saifhashemi Hossein Pedram The Pennsylvania State University CiteSeerX Archives

Source: http://www.cecs.uci.edu/~papers/compendium94-03/papers/2003/dac03/pdffiles/20_3.pdf.

Subject Terms: B.6.1 [Logic Design, Design Styles–Asynchronous circuits, Parallel circuits, D.1.3 [Programming Techniques, Concurrent Programming–CSP, B.6.3 [Logic Design, Design Aids– Hardware description languages, Simulation, Verilog, PLI. General Terms Design, Languages. Keywords Asynchronous circuits, CSP, CHP, PLI, Channel

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Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.637.5030

Availability: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.637.5030
http://www.cecs.uci.edu/~papers/compendium94-03/papers/2003/dac03/pdffiles/20_3.pdf

20.3 Verilog HDL, Powered by PLI: a Suitable Framework for Describing and Modeling Asynchronous Circuits at All Levels of Abstraction

Authors: Arash Saifhashemi Hossein Pedram The Pennsylvania State University CiteSeerX Archives

Contributors: Arash Saifhashemi Hossein Pedram The Pennsylvania State University CiteSeerX Archives

Source: http://ceit.aut.ac.ir/~pedram/Papers/Paper-DAC2003-PLI.pdf.

Subject Terms: B.6.1 [Logic Design, Design Styles–Asynchronous circuits, Parallel circuits, D.1.3 [Programming Techniques, Concurrent Programming–CSP, B.6.3 [Logic Design, Design Aids– Hardware description languages, Simulation, Verilog, PLI. General Terms Design, Languages. Keywords Asynchronous circuits, CSP, CHP, PLI, Channel

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Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.424.2587

Availability: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.424.2587
http://ceit.aut.ac.ir/~pedram/Papers/Paper-DAC2003-PLI.pdf

Nanomagnetic Logic Microprocessor: Hierarchical Power Model.

Authors: Vacca, Marco Graziano, Mariagrazia Zamboni, Maurizio

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Aug2013, Vol. 21 Issue 8, p1410-1420, 11p

Subject Terms: INTEGRATED circuits, COMPUTER hardware description languages, NANOMAGNETICS, MICROPROCESSORS, NANOTECHNOLOGY, COMPLEMENTARY metal oxide semiconductors, ENERGY dissipation

INVITED: RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs.

Authors: Heechun Park Kyungwook Chang Bon Woong Ku et al.

Source: DAC: Annual ACM/IEEE Design Automation Conference; 2019, Issue 56, p1281-1284, 4p

Subject Terms: NONVOLATILE random-access memory, DATA integrity, NONVOLATILE memory, LOGIC circuits, ELECTRONIC design automation

Design and architecture for an embedded 32-bit QueueCore.

Authors: Abderazek, Ben A. Kawata, Sotaro Sowa, Masahiro

Source: Journal of Embedded Computing; 2006, Vol. 2 Issue 2, p191-205, 15p, 1 Black and White Photograph, 8 Diagrams, 2 Charts, 4 Graphs

Subject Terms: EMBEDDED computer systems, INTEGRATED circuits, COMPUTER architecture, MICROPROCESSORS, PROGRAMMABLE logic devices

Design of Efficient Reversible Logic-Based Binary and BCD Adder Circuits.

Authors: THAPLIYAL, HIMANSHU RANGANATHAN, NAGARAJAN

Source: ACM Journal on Emerging Technologies in Computing Systems; Sep2013, Vol. 9 Issue 3, p17:1-17:31, 31p

Subject Terms: QUANTUM computing, COMPUTER input-output equipment design & construction, BINARY codes, BINARY-coded decimal system, CLOUD computing

Applying Genetic Parallel Programming to Synthesize Combinational Logic Circuits.

Authors: Sin Man Cheang Kin Hong Lee Kwong Sak Leung

Source: IEEE Transactions on Evolutionary Computation; Aug2007, Vol. 11 Issue 4, p503-520, 18p

Subject Terms: EVOLUTIONARY computation, GENETIC programming, PARALLEL programming, DIGITAL electronics, LOGIC circuits, LOGIC design

On the Implementation of Computation-in-Memory Parallel Adder.

Authors: Du Nguyen, Hoang Anh Xie, Lei Taouil, Mottaqiallah et al.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Aug2017, Vol. 25 Issue 8, p2206-2219, 14p

Subject Terms: CMOS memory circuits, LOGIC circuits, COMPUTER integrated manufacturing systems, IMPLICATION (Logic), ADDERS (Digital electronics)

The Benefits of Using Variable-Length Pipelined Operations in High-Level Synthesis.

Authors: BEN-ASHER, YOSI ROTEM, NADAV

Source: ACM Transactions on Embedded Computing Systems; Dec2013, Vol. 13 Issue 3, p52:1-52:23, 23p

Subject Terms: VARIABLE-length codes, HIGH level synthesis (Electronic design), ARITHMETIC, RESOURCE management, INTEGRATED circuits, PARALLEL computers

Emerging tunnel FET and spintronics-based hardware-secure circuit design with ultra-low energy consumption.

Authors: Japa, Aditya Sahoo, Subhendu K. Vaddi, Ramesh et al.

Source: Journal of Computational Electronics; Feb2023, Vol. 22 Issue 1, p178-189, 12p

A Study of Asynchronous Design Methodology for Robust CMOS-Nano Hybrid System Design.

Authors: Chakraborty, Rajat Subhra Bhunia, Swarup

Source: ACM Journal on Emerging Technologies in Computing Systems; 2009, Vol. 5 Issue 3, p12.1-12:22, 22p, 8 Diagrams, 4 Charts, 1 Graph

Subject Terms: COMPLEMENTARY metal oxide semiconductors, MOLECULAR integrated circuits, LOGIC circuit design, METHODOLOGY, SYSTEMS design, DIGITAL electronics, SWITCHING circuits

Design of High-Speed Logic Circuits with Four-Step RRAM-Based Logic Gates.

Authors: Cui, Xiaole Ma, Xiao Lin, Qiujun et al.

Source: Circuits, Systems & Signal Processing; Jun2020, Vol. 39 Issue 6, p2822-2840, 19p

Subject Terms: SEQUENTIAL circuits, COMBINATIONAL circuits, LOGIC circuit design, PARALLEL electric circuits, LOGIC circuits

Ultra-Low-Leakage Chip Multiprocessor Design with Hybrid FinFET Logic Styles.

Authors: XIANMIN CHEN JHA, NIRAJ K.

Source: ACM Journal on Emerging Technologies in Computing Systems; Sep2014, Vol. 11 Issue 1, p1-16, 16p

Subject Terms: COMPLEMENTARY metal oxide semiconductors, MULTIPROCESSORS, ENERGY consumption research, INTEGRATED circuits, COMPUTER systems

A taxonomy of design styles.

Authors: Beerel, Peter A. Ozdag, Recep O. Ferretti, Marcos

Source: Designer's Guide to Asynchronous VLSI; 2010, p116-135, 20p