Search Results - ACM: B.: Hardware/B.3: MEMORY STRUCTURES/B.3.2: Design Styles~
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Authors: et al.
Contributors: et al.
Source: https://inria.hal.science/inria-00426765 ; [Research Report] RR-7073, INRIA. 2009.
Subject Terms: Compressed Memory, Null Block, Zero Blocks, ACM: B.: Hardware/B.3: MEMORY STRUCTURES/B.3.2: Design Styles, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]
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ATLB Improvements for Chip Multiprocessors: Inter-Core Cooperative Prefetchers and Shared Last-Level
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Subject Terms: Categories and Subject Descriptors, B.3.2 [Hardware, Memory Structures—Design Styles, C.1.2 [Computer Systems Organization, Processor Architectures—Multiple Data Stream Architectures (Multiprocessors) General Terms, Design, Experimentation, Measurement, Performance Additional Key Words and Phrases, Translation Lookaside Buffer, Shared Last-Level TLB, TLB Prefetching, Simulation, Performance Evaluation ACM Reference Format
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Authors: et al.
Contributors: et al.
Subject Terms: Categories and Subject Descriptors, B.3.2 [Memory Structures, Design Styles, C.1.2 [Processor Architectures, Multiple Data Stream Architectures (Multiprocessors, D.1.3 [Programming Techniques, Concurrent Programming General Terms, Performance, Design Additional Key Words and Phrases, Chip multiprocessors, cache coherence, streaming memory, parallel programming, locality optimizations ACM Reference Format
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Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.365.3079; http://csl.stanford.edu/~christos/publications/2008.pmarch.taco.pdf
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Authors: et al.
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Source: FCCM - 22nd IEEE International Symposium on Field-Programmable Custom Computing Machines ; https://inria.hal.science/hal-01017185 ; FCCM - 22nd IEEE International Symposium on Field-Programmable Custom Computing Machines, May 2014, Boston, United States. pp.230-233, ⟨10.1109/FCCM.2014.68⟩
Subject Terms: Low power, microcontrollers, power gating, reconfigurable hardware, wireless sensor networks, ACM: B.: Hardware/B.1: CONTROL STRUCTURES AND MICROPROGRAMMING, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI]
Subject Geographic: Boston, United States
Time: Boston, United States
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Authors: et al.
Contributors: et al.
Subject Terms: Categories and Subject Descriptors, B.3.2 [Memory Structures, Design Styles-interleaved memories, 1.3. I [Computer Graphics, Hardware Architecture-raster display devices General Terms, Design, Performance, Theory Additional Key Words and Phrases, BITBLT, Fibonacci lattices, golden ratio, interleaving, memory organization
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Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.106.6105; http://www.cs.technion.ac.il/~benny/Raster.pdf
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Authors: et al.
Contributors: et al.
Subject Terms: B.3.2 [Memory Structures, Design Styles–Cache Memories
File Description: application/pdf
Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.169.5313; http://www.cs.utah.edu/%7Erajeev/pubs/pact10p.pdf
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Authors: et al.
Contributors: et al.
Subject Terms: Categories and Subject Descriptors, B.3.2 [Memory Structures, Design Styles—cache memories, C.0 [General, Modeling of Computer Architecture General Terms, Design, Cache, Memory, Performance, Simulation Additional Key Words and Phrases, LLC, insertion policy, replacement policy, main memory, bandwidth, sampling ACM Reference Format
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Authors: et al.
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Subject Terms: Categories and Subject Descriptors, B.3.2 [Memory Structures, Design Styles—Cache memories, B.3.3 [Memory Structures, Performance Analysis and Design Aids—Simulation, D.3.4 [Programming Languages, Processors—Optimization General Terms, Experimentation, Performance Additional Key Words and Phrases, Prefetching, cache ACM Reference Format
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Authors: et al.
Contributors: et al.
Subject Terms: Categories and Subject Descriptors, B.3.2 [Memory Structures, Design Styles-interleaved 1.3. I [Computer Graphics, Hardware Architecture-raster display devices General Terms, Design, Performance, Theory memories, Additional Key Words and Phrases, BITBLT, Fibonacci lattices, golden ratio, interleaving, memory
File Description: application/pdf
Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.310.144; http://people.csail.mit.edu/rivest/pubs/CLRS86.pdf
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Authors: et al.
Contributors: et al.
Subject Terms: Categories and Subject Descriptors, C.3 [Special-Purpose and Application-Based Systems, C.1.3 [Processor Architectures, Other Architecture Styles—Heterogeneous (hybrid) Systems General Terms, Design, Performance, Management Additional Key Words and Phrases, Hardware acceleration, memory systems, shared memory, low power ACM Reference Format
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Authors: et al.
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Source: International Conference on Compilers, Architecture and Synthesis for Embedded Systems ; https://ensta.hal.science/hal-01108053 ; International Conference on Compilers, Architecture and Synthesis for Embedded Systems, Karam S. Chatha (Qualcomm Research); Rolf Ernst (TU Braunschweig), Oct 2014, New Delhi, India. pp.10, ⟨10.1145/2656106.2656128⟩ ; http://esweek.acm.org/esweek2014/cases
Subject Terms: single-entry region, real-time systems, method cache, graph partitioning, function splitting, ACM: B.: Hardware/B.3: MEMORY STRUCTURES/B.3.2: Design Styles, [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL], [INFO.INFO-PF]Computer Science [cs]/Performance [cs.PF]
Relation: info:eu-repo/grantAgreement//288008/EU/Time-predictable Multi-Core Architecture for Embedded Systems/T-CREST
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Subject Terms: and queues, B.3.2 [Hardware, Memory Structures—Design Styles
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Authors: et al.
Source: Journal of Supercomputing; Jun2015, Vol. 71 Issue 6, p2309-2338, 30p
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Authors: et al.
Source: Data Science & Engineering; Sep2018, Vol. 3 Issue 3, p263-276, 14p
Subject Terms: DATA analysis, INFORMATION technology, HARDWARE, COMPUTER software development, NONVOLATILE memory
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Authors: et al.
Contributors: et al.
Subject Terms: Categories and Subject Descriptors, B.3.2 [Memory Structures, Design Styles—cache memo- ries, shared memory, virtual memory, C. 1.2 [Processor Architectures, Multiple Data Stream Architectures (Multiprocessors)—intercormection architectures, parallel processors, D.4.2 [Oper- ating Systems, Storage Management—distributed memories, D.4.4 [Operat- ing Systems, Communications Management—network communication, D.4.7 [Operating Systems, Organization and Design—distributed systems, D.4.8 [Operating Systems, Perfor- mance—measuremen ts
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Source: International Symposium on System Synthesis (IEEE Cat. No.01EX526); 2001, p101-106, 6p
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Authors: et al.
Source: Intelligent Automation & Soft Computing; 2022, Vol. 33 Issue 3, p1665-1675, 11p
Subject Terms: MEMORY, ARITHMETIC, REVERSE engineering, HARDWARE, LOGIC
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Authors: et al.
Source: ACM Computing Surveys; Nov2020, Vol. 52 Issue 6, p1-39, 39p
Subject Terms: ARCHITECTURAL design, TAXONOMY, ENERGY consumption
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Source: ACM Transactions on Embedded Computing Systems; Nov2025, Vol. 24 Issue 6, p1-25, 25p
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Authors: et al.
Contributors: et al.
Subject Terms: B.3.2 [Hardware, Design Styles of Memory Structures – cache memories. General Terms, Algorithms, Management, Measurement, Performance, Design, Experimentation Keywords, Quality of Service, CMP, Cache/Memory, Service Level Agreements, Resource Sharing
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