Search Results - ACM: B.: Hardware/B.3: MEMORY STRUCTURES/B.3.2: Design Styles/B.3.2.1: Cache memories
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Authors: et al.
Contributors: et al.
Subject Terms: Categories and Subject Descriptors, B.3.2 [Memory Structures, Design Styles, C.1.2 [Processor Architectures, Multiple Data Stream Architectures (Multiprocessors, D.1.3 [Programming Techniques, Concurrent Programming General Terms, Performance, Design Additional Key Words and Phrases, Chip multiprocessors, cache coherence, streaming memory, parallel programming, locality optimizations ACM Reference Format
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Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.365.3079; http://csl.stanford.edu/~christos/publications/2008.pmarch.taco.pdf
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Authors: et al.
Contributors: et al.
Source: https://inria.hal.science/inria-00426765 ; [Research Report] RR-7073, INRIA. 2009.
Subject Terms: Compressed Memory, Null Block, Zero Blocks, ACM: B.: Hardware/B.3: MEMORY STRUCTURES/B.3.2: Design Styles, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]
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Authors: et al.
Contributors: et al.
Subject Terms: Categories and Subject Descriptors, B.3.2 [Memory Structures, Design Styles—cache memories, C.0 [General, Modeling of Computer Architecture General Terms, Design, Cache, Memory, Performance, Simulation Additional Key Words and Phrases, LLC, insertion policy, replacement policy, main memory, bandwidth, sampling ACM Reference Format
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Source: International Journal of Parallel, Emergent & Distributed Systems; Aug2020, Vol. 35 Issue 4, p483-491, 9p
Subject Terms: ABORTION, MEMORY, PERFORMANCES, COMPUTER memory management, TRANSACTION systems (Computer systems), HARDWARE
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Authors: et al.
Contributors: et al.
Subject Terms: B.3.2 [Hardware, Design Styles of Memory Structures – cache memories. General Terms, Algorithms, Management, Measurement, Performance, Design, Experimentation Keywords, Quality of Service, CMP, Cache/Memory, Service Level Agreements, Resource Sharing
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Authors: et al.
Contributors: et al.
Subject Terms: B.3.2 [Memory Structures, Design Styles–Cache Memories
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Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.169.5313; http://www.cs.utah.edu/%7Erajeev/pubs/pact10p.pdf
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Authors: et al.
Source: IEEE Micro; Jan/Feb2010, Vol. 30 Issue 1, p29-39, 11p, 4 Diagrams, 2 Graphs
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Source: ACM Transactions on Embedded Computing Systems; Mar2014, Vol. 13 Issue Supp 4, p1-25, 25p
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Authors: et al.
Contributors: et al.
Subject Terms: Categories and Subject Descriptors, B.3.2 [Memory Structures, Design Styles—cache memo- ries, shared memory, virtual memory, C. 1.2 [Processor Architectures, Multiple Data Stream Architectures (Multiprocessors)—intercormection architectures, parallel processors, D.4.2 [Oper- ating Systems, Storage Management—distributed memories, D.4.4 [Operat- ing Systems, Communications Management—network communication, D.4.7 [Operating Systems, Organization and Design—distributed systems, D.4.8 [Operating Systems, Perfor- mance—measuremen ts
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Authors: et al.
Source: ACM Transactions on Embedded Computing Systems; Feb2015, Vol. 14 Issue 2, p1-26, 26p
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Source: ACM Transactions on Embedded Computing Systems; Apr2015, Vol. 14 Issue 3, p53:1-53:25, 25p
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Authors: et al.
Source: ACM Transactions on Embedded Computing Systems; Aug2022, Vol. 21 Issue 4, p1-21, 21p
Subject Terms: DYNAMIC random access memory, COMPUTER storage devices, CACHE memory, ENERGY consumption, BIG data
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Contributors:
Subject Terms: Categories and Subject Descriptors, B.3.2 [Memory Structures, Design Styles—Shared memory, C.0 [General, Hardware/Software interfaces, C.1.2 [Processor Architectures, Multiprocessors, D.2.0 [Software Engineering, General — Protection mechanisms General Terms, Performance, Design, Reliability, Security Keywords, Access control, Cache coherence, Memory protection, Sentry, Protection domains, Safety
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Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.298.4116; http://www.cs.rochester.edu/u/sandhya/papers/isca10.pdf
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Authors: et al.
Source: IEEE Micro; Jul/Aug2008, Vol. 28 Issue 4, p51-70, 20p
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Authors: et al.
Source: Fundamental Research; May2024, Vol. 4 Issue 3, p651-659, 9p
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Source: ACM Transactions on Embedded Computing Systems; Apr2009, Vol. 8 Issue 3, p21-21-31, 31p, 9 Diagrams, 1 Chart, 14 Graphs
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Source: International Symposium on System Synthesis (IEEE Cat. No.01EX526); 2001, p101-106, 6p
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Contributors: The Pennsylvania State University CiteSeerX Archives
Subject Terms: Categories and Subject Descriptors, F.2.2 [Theory of Computation, Analysis of Algorithms and Problem Complexity--Nonnumerical Algorithms and Problems, E.5 [Data, Files--Sorting/searching, D.1.0 [Software, Programming Techniques--General, B.3.2 [Hardware, Memory Structures--Design Styles General Terms, Efficient sorting algorithms, Locality of reference, Radix sort, Memory hierarchy, External-memory algorithms Key Words and Phrases, Cache, Translation-lookaside buffer (TLB
File Description: application/postscript
Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.65.7331; http://www.dcs.kcl.ac.uk/pg/naila/papers/ALENEX2000.ps.gz
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Authors: et al.
Source: ACM Transactions on Embedded Computing Systems; Nov2024, Vol. 23 Issue 6, p1-34, 34p
Subject Terms: RESEARCH personnel, METADATA, DURABILITY, MEMORY, HARDWARE, CACHE memory
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Contributors: The Pennsylvania State University CiteSeerX Archives
Subject Terms: Categories and Subject Descriptors, F.2.2 [Theory of Computation, Analysis of Algorithms and Problem Complexity--Nonnumerical Algorithms and Problems, E.5 [Data, Files--Sorting/searching, D.1.0 [Software, Programming Techniques--General, B.3.2 [Hardware, Memory Structures--Design Styles General Terms, Efficient sorting algorithms, Locality of reference, Radix sort, Memory hierarchy, External-memory algorithms Additional Key Words and Phrases, Cache, Translation-lookaside buffer (TLB
File Description: application/postscript
Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.65.7141; http://www.dcs.kcl.ac.uk/pg/naila/papers/JEA2001.ps.gz
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