Výsledky vyhledávání - ACM: B.: Hardware/B.3: MEMORY STRUCTURES/B.3.2: Design Styles*

Decoupled Zero-Compressed Memory

Autoři: Dusser, Julien Seznec, André Amdahl's Law is Forever (ALF) a další

Přispěvatelé: Dusser, Julien Seznec, André Amdahl's Law is Forever (ALF) a další

Zdroj: https://inria.hal.science/inria-00426765 ; [Research Report] RR-7073, INRIA. 2009.

Témata: Compressed Memory, Null Block, Zero Blocks, ACM: B.: Hardware/B.3: MEMORY STRUCTURES/B.3.2: Design Styles, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Dostupnost: https://inria.hal.science/inria-00426765
https://inria.hal.science/inria-00426765/document
https://inria.hal.science/inria-00426765/file/DZC_Memory.RR.pdf

ATLB Improvements for Chip Multiprocessors: Inter-Core Cooperative Prefetchers and Shared Last-Level

Autoři: Daniel Lustig The Pennsylvania State University CiteSeerX Archives

Přispěvatelé: Daniel Lustig The Pennsylvania State University CiteSeerX Archives

Zdroj: http://www.cs.rutgers.edu/~abhib/dlustig-taco13.pdf.

Témata: Categories and Subject Descriptors, B.3.2 [Hardware, Memory Structures—Design Styles, C.1.2 [Computer Systems Organization, Processor Architectures—Multiple Data Stream Architectures (Multiprocessors) General Terms, Design, Experimentation, Measurement, Performance Additional Key Words and Phrases, Translation Lookaside Buffer, Shared Last-Level TLB, TLB Prefetching, Simulation, Performance Evaluation ACM Reference Format

Popis souboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.592.1051

Dostupnost: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.592.1051
http://www.cs.rutgers.edu/~abhib/dlustig-taco13.pdf

12 Comparative Evaluation of Memory Models for Chip Multiprocessors

Autoři: Jacob Leverich Hideho Arakida Alex Solomatnikov a další

Přispěvatelé: Jacob Leverich Hideho Arakida Alex Solomatnikov a další

Zdroj: http://csl.stanford.edu/~christos/publications/2008.pmarch.taco.pdf.

Témata: Categories and Subject Descriptors, B.3.2 [Memory Structures, Design Styles, C.1.2 [Processor Architectures, Multiple Data Stream Architectures (Multiprocessors, D.1.3 [Programming Techniques, Concurrent Programming General Terms, Performance, Design Additional Key Words and Phrases, Chip multiprocessors, cache coherence, streaming memory, parallel programming, locality optimizations ACM Reference Format

Popis souboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.365.3079; http://csl.stanford.edu/~christos/publications/2008.pmarch.taco.pdf

Dostupnost: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.365.3079
http://csl.stanford.edu/~christos/publications/2008.pmarch.taco.pdf

Low Power Reconfigurable Controllers for Wireless Sensor Network Nodes

Autoři: Tovinakere Dwarakanath, Vivek Sentieys, Olivier Derrien, Steven a další

Přispěvatelé: Tovinakere Dwarakanath, Vivek Sentieys, Olivier Derrien, Steven a další

Zdroj: FCCM - 22nd IEEE International Symposium on Field-Programmable Custom Computing Machines ; https://inria.hal.science/hal-01017185 ; FCCM - 22nd IEEE International Symposium on Field-Programmable Custom Computing Machines, May 2014, Boston, United States. pp.230-233, ⟨10.1109/FCCM.2014.68⟩

Témata: Low power, microcontrollers, power gating, reconfigurable hardware, wireless sensor networks, ACM: B.: Hardware/B.1: CONTROL STRUCTURES AND MICROPROGRAMMING, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI]

Geografické téma: Boston, United States

Time: Boston, United States

Dostupnost: https://inria.hal.science/hal-01017185
https://inria.hal.science/hal-01017185v1/document
https://inria.hal.science/hal-01017185v1/file/tovinakere-fccm14.pdf
https://doi.org/10.1109/FCCM.2014.68

An application of number theory to the organization of raster-graphics memory

Autoři: Benny Chor Charles E. Leiserson Ronald L. Rivest a další

Přispěvatelé: Benny Chor Charles E. Leiserson Ronald L. Rivest a další

Zdroj: http://www.cs.technion.ac.il/~benny/Raster.pdf.

Témata: Categories and Subject Descriptors, B.3.2 [Memory Structures, Design Styles-interleaved memories, 1.3. I [Computer Graphics, Hardware Architecture-raster display devices General Terms, Design, Performance, Theory Additional Key Words and Phrases, BITBLT, Fibonacci lattices, golden ratio, interleaving, memory organization

Popis souboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.106.6105; http://www.cs.technion.ac.il/~benny/Raster.pdf

Dostupnost: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.106.6105
http://www.cs.technion.ac.il/~benny/Raster.pdf

SWEL: Hardware Cache Coherence Protocols to Map Shared Data onto Shared Caches ∗

Autoři: Seth H. Pugsley Josef B. Spjut David W. Nellans a další

Přispěvatelé: Seth H. Pugsley Josef B. Spjut David W. Nellans a další

Zdroj: http://www.cs.utah.edu/%7Erajeev/pubs/pact10p.pdf.

Témata: B.3.2 [Memory Structures, Design Styles–Cache Memories

Popis souboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.169.5313; http://www.cs.utah.edu/%7Erajeev/pubs/pact10p.pdf

Dostupnost: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.169.5313
http://www.cs.utah.edu/%7Erajeev/pubs/pact10p.pdf

0ARI: Adaptive LLC-Memory Traffic Management

Autoři: Viacheslav V. Fedorov Texas A Paul V. Gratz a další

Přispěvatelé: Viacheslav V. Fedorov Texas A Paul V. Gratz a další

Zdroj: http://cesg.tamu.edu/wp-content/uploads/2012/02/TACO_ARI_submitted.pdf.

Témata: Categories and Subject Descriptors, B.3.2 [Memory Structures, Design Styles—cache memories, C.0 [General, Modeling of Computer Architecture General Terms, Design, Cache, Memory, Performance, Simulation Additional Key Words and Phrases, LLC, insertion policy, replacement policy, main memory, bandwidth, sampling ACM Reference Format

Popis souboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.650.146

Dostupnost: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.650.146
http://cesg.tamu.edu/wp-content/uploads/2012/02/TACO_ARI_submitted.pdf

When Prefetching Works, When It Doesn’t, and Why

Autoři: Jaekyu Lee Hyesoon Kim Richard Vuduc a další

Přispěvatelé: Jaekyu Lee Hyesoon Kim Richard Vuduc a další

Zdroj: http://vuduc.org/pubs/lee2012-taco.pdf.

Témata: Categories and Subject Descriptors, B.3.2 [Memory Structures, Design Styles—Cache memories, B.3.3 [Memory Structures, Performance Analysis and Design Aids—Simulation, D.3.4 [Programming Languages, Processors—Optimization General Terms, Experimentation, Performance Additional Key Words and Phrases, Prefetching, cache ACM Reference Format

Popis souboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.298.2743

Dostupnost: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.298.2743
http://vuduc.org/pubs/lee2012-taco.pdf

AND

Autoři: Benny Chor Charles E. Leiserson Ronald a další

Přispěvatelé: Benny Chor Charles E. Leiserson Ronald a další

Zdroj: http://people.csail.mit.edu/rivest/pubs/CLRS86.pdf.

Témata: Categories and Subject Descriptors, B.3.2 [Memory Structures, Design Styles-interleaved 1.3. I [Computer Graphics, Hardware Architecture-raster display devices General Terms, Design, Performance, Theory memories, Additional Key Words and Phrases, BITBLT, Fibonacci lattices, golden ratio, interleaving, memory

Popis souboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.310.144; http://people.csail.mit.edu/rivest/pubs/CLRS86.pdf

Dostupnost: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.310.144
http://people.csail.mit.edu/rivest/pubs/CLRS86.pdf

The Accelerator Store: A Shared Memory Framework For Accelerator-Based Systems

Autoři: Michael J. Lyons Gu-yeon Wei David Brooks a další

Přispěvatelé: Michael J. Lyons Gu-yeon Wei David Brooks a další

Zdroj: http://www.eecs.harvard.edu/%7Emjlyons/papers/lyons-accelerator-store-taco-2012.pdf.

Témata: Categories and Subject Descriptors, C.3 [Special-Purpose and Application-Based Systems, C.1.3 [Processor Architectures, Other Architecture Styles—Heterogeneous (hybrid) Systems General Terms, Design, Performance, Management Additional Key Words and Phrases, Hardware acceleration, memory systems, shared memory, low power ACM Reference Format

Popis souboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.226.994

Dostupnost: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.226.994
http://www.eecs.harvard.edu/%7Emjlyons/papers/lyons-accelerator-store-taco-2012.pdf

Splitting functions into single-entry regions

Autoři: Hepp, Stefan Brandner, Florian Vienna University of Technology = Technische Universität Wien (TU Wien) a další

Přispěvatelé: Hepp, Stefan Brandner, Florian Vienna University of Technology = Technische Universität Wien (TU Wien) a další

Zdroj: International Conference on Compilers, Architecture and Synthesis for Embedded Systems ; https://ensta.hal.science/hal-01108053 ; International Conference on Compilers, Architecture and Synthesis for Embedded Systems, Karam S. Chatha (Qualcomm Research); Rolf Ernst (TU Braunschweig), Oct 2014, New Delhi, India. pp.10, ⟨10.1145/2656106.2656128⟩ ; http://esweek.acm.org/esweek2014/cases

Témata: single-entry region, real-time systems, method cache, graph partitioning, function splitting, ACM: B.: Hardware/B.3: MEMORY STRUCTURES/B.3.2: Design Styles, [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL], [INFO.INFO-PF]Computer Science [cs]/Performance [cs.PF]

Geografické téma: New Delhi, India

Relation: info:eu-repo/grantAgreement//288008/EU/Time-predictable Multi-Core Architecture for Embedded Systems/T-CREST

Dostupnost: https://ensta.hal.science/hal-01108053
https://doi.org/10.1145/2656106.2656128

Cacheoblivious shortest paths in graphs using buffer heap

Autoři: Rezaul Alam Chowdhury Vijaya Ramachandran The Pennsylvania State University CiteSeerX Archives

Přispěvatelé: Rezaul Alam Chowdhury Vijaya Ramachandran The Pennsylvania State University CiteSeerX Archives

Zdroj: http://www.cs.utexas.edu/~shaikat/papers/SSSP-SPAA-04.pdf.

Témata: and queues, B.3.2 [Hardware, Memory Structures—Design Styles

Popis souboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.331.9381

Dostupnost: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.331.9381
http://www.cs.utexas.edu/~shaikat/papers/SSSP-SPAA-04.pdf

Architectural support for task scheduling: hardware scheduling for dataflow on NUMA systems.

Autoři: Khan, Behram Goodman, Daniel Khan, Salman a další

Zdroj: Journal of Supercomputing; Jun2015, Vol. 71 Issue 6, p2309-2338, 30p

Témata: DATA flow computing, NON-uniform memory access, COMPUTER software, QUEUEING networks, FIRST in, first out (Queuing theory)

The New Hardware Development Trend and the Challenges in Data Management and Analysis.

Autoři: Pan, Wei Li, Zhanhuai Zhang, Yansong a další

Zdroj: Data Science & Engineering; Sep2018, Vol. 3 Issue 3, p263-276, 14p

Témata: DATA analysis, INFORMATION technology, HARDWARE, COMPUTER software development, NONVOLATILE memory

Techniques for reducing consistency-related communications in distributed shared memory systems

Autoři: John B. Carter John K. Bennett Willy Zwaenepoel a další

Přispěvatelé: John B. Carter John K. Bennett Willy Zwaenepoel a další

Zdroj: http://www.csie.fju.edu.tw/~yeh/research/papers/os-reading-list/carter-tocs95-dsm.pdf.

Témata: Categories and Subject Descriptors, B.3.2 [Memory Structures, Design Styles—cache memo- ries, shared memory, virtual memory, C. 1.2 [Processor Architectures, Multiple Data Stream Architectures (Multiprocessors)—intercormection architectures, parallel processors, D.4.2 [Oper- ating Systems, Storage Management—distributed memories, D.4.4 [Operat- ing Systems, Communications Management—network communication, D.4.7 [Operating Systems, Organization and Design—distributed systems, D.4.8 [Operating Systems, Perfor- mance—measuremen ts

Popis souboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.452.6724

Dostupnost: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.452.6724
http://www.csie.fju.edu.tw/~yeh/research/papers/os-reading-list/carter-tocs95-dsm.pdf

Cache-efficient memory layout of aggregate data structures.

Autoři: Panda, P.R. Semeria, L. de Micheli, G.

Zdroj: International Symposium on System Synthesis (IEEE Cat. No.01EX526); 2001, p101-106, 6p

Design of Logically Obfuscated Memory and Arithmetic Logic Unit for Improved Hardware Security.

Autoři: Usharani, M. Sakthivel, B. Jayaram, K. a další

Zdroj: Intelligent Automation & Soft Computing; 2022, Vol. 33 Issue 3, p1665-1675, 11p

Témata: MEMORY, ARITHMETIC, REVERSE engineering, HARDWARE, LOGIC

A Survey of Coarse-Grained Reconfigurable Architecture and Design: Taxonomy, Challenges, and Applications.

Autoři: LEIBO LIU JIANFENG ZHU ZHAOSHI LI a další

Zdroj: ACM Computing Surveys; Nov2020, Vol. 52 Issue 6, p1-39, 39p

Témata: ARCHITECTURAL design, TAXONOMY, ENERGY consumption

Unlocking the Full Potential of Dual-Interface SSDs: A Comprehensive Hardware and Software Perspective.

Autoři: Chow, Lok Yin Wang, Yingjia Liang, Yuhong a další

Zdroj: ACM Transactions on Embedded Computing Systems; Nov2025, Vol. 24 Issue 6, p1-25, 25p

Témata: FLASH memory, COMPUTER storage devices, MATHEMATICAL optimization, NONVOLATILE random-access memory, SYSTEM integration, DATA structures

QoS Policy and Architecture for Cache/Memory in CMP Platforms

Autoři: Ravi Iyer Li Zhao Fei Guo a další

Přispěvatelé: Ravi Iyer Li Zhao Fei Guo a další

Zdroj: http://www.ece.ncsu.edu/arpers/Papers/qos-sig07.pdf.

Témata: B.3.2 [Hardware, Design Styles of Memory Structures – cache memories. General Terms, Algorithms, Management, Measurement, Performance, Design, Experimentation Keywords, Quality of Service, CMP, Cache/Memory, Service Level Agreements, Resource Sharing

Popis souboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.86.5287

Dostupnost: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.86.5287
http://www.ece.ncsu.edu/arpers/Papers/qos-sig07.pdf