Výsledky vyhledávání - 3-D processor array

Efficient 3-D Processor Array Reconfiguration Algorithms Based on Bucket Effect

Autoři: Hao Ding Yanlong He Zhongyi Zhai a další

Zdroj: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 43:1023-1036

Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array

INTERCONNECT CIRCUITS AT THREE-DIMENSIONAL (3-D) BONDING INTERFACES OF A PROCESSOR ARRAY

Interconnect circuits at three dimensional (3-D) bonding interfaces of a processor array

INTERCONNECT CIRCUITS AT THREE DIMENSIONAL (3-D) BONDING INTERFACES OF A PROCESSOR ARRAY

Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array

INTERCONNECT CIRCUITS AT THREE-DIMENSIONAL (3-D) BONDING INTERFACES OF A PROCESSOR ARRAY

Efficient Reconfiguration Algorithm With Flexible Rerouting Schemes for Constructing 3-D VLSI Subarrays.

Autoři: Qian, Junyan Ding, Hao Xiao, Hanpeng a další

Zdroj: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Jan2020, Vol. 39 Issue 1, p267-271, 5p

Témata: ALGORITHMS, VERY large scale circuit integration, HEURISTIC algorithms, GROUND penetrating radar, ARRAY processors, HEURISTIC programming

A Fast Processor for 3-D Device Simulation Using Systolic Arrays.

Autoři: Naritomi, Takashi Aso, Hirotomo Kimura, Masayuki

Zdroj: Systems & Computers in Japan. 1/1/91, Vol. 22 Issue 1, p39-48. 10p.

Témata: Systolic array circuits, Wafer-scale integration of circuits, Very large scale circuit integration, Semiconductors, Parallel processing, Electronic data processing

High resolution and frame rate image signal processor array design for 3-D imager.

Autoři: Cheng, Chang-Hsin Hsieh, Hsien-Ching Fan, Tso-Yi a další

Zdroj: 2012 International Symposium on Intelligent Signal Processing & Communications Systems; 1/ 1/2012, p735-739, 5p

End-to-End Implementation of a Convolutional Neural Network on a 3D-Integrated Image Sensor with Macropixel Array.

Autoři: Lepecq, Maria Dalgaty, Thomas Fabre, William a další

Zdroj: Sensors (14248220); Feb2023, Vol. 23 Issue 4, p1909, 15p

Témata: CONVOLUTIONAL neural networks, SENSOR arrays, COMPUTER vision, ARRAY processors, IMAGE sensors, SIMPLE machines

A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration.

Autoři: Zia, Aamir Jacob, Philip Jin-Woo Kim a další

Zdroj: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Jun2010, Vol. 18 Issue 6, p967-977, 11p

Témata: BANDWIDTHS, COMPLEMENTARY metal oxide semiconductors, MICROPROCESSORS, SEMICONDUCTOR wafers, CACHE memory

Orbital Systolic Algorithms and Array Processors for Solution of the Algebraic Path Problem

Autoři: Kenichi KURODA Stanislav G. SEDUKHIN Toshiaki MIYAZAKI

Zdroj: IEICE Transactions on Information and Systems. 2010, E93.D(3):534

Design Space Exploration of 2-D Processor Array Architectures for Similarity Distance Computation.

Autoři: Kanan, Awos Gebali, Fayez Ibrahim, Atef

Zdroj: IEEE Transactions on Parallel & Distributed Systems. Aug2017, Vol. 28 Issue 8, p2218-2228. 11p.

Témata: *SPACE exploration, *COMPUTATIONAL complexity, *MACHINE learning, *AD hoc computer networks, *ALGORITHMS

Design Techniques to Facilitate Processor Power Delivery in 3-D Processor-DRAM Integrated Systems.

Autoři: Wu, Qi Zhang, Tong

Zdroj: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Sep2011, Vol. 19 Issue 9, p1655-1666, 12p

Témata: RANDOM access memory, CAPACITORS, ELECTRONIC packaging, COMPUTER simulation, SIGNAL processing, ENERGY consumption, MICROFABRICATION, INTEGRATED circuits

A hardware-efficient on-implant spike compression processor based on VQ-DAE for brain-implantable microsystems.

Autoři: Ahmadi-Dastgerdi N Hosseini-Nejad H Alinejad-Rokny H

Zdroj: Medical & biological engineering & computing [Med Biol Eng Comput] 2025 Jul; Vol. 63 (7), pp. 2047-2056. Date of Electronic Publication: 2025 Feb 08.

Způsob vydávání: Journal Article

Informace o časopise: Publisher: Springer Country of Publication: United States NLM ID: 7704869 Publication Model: Print-Electronic Cited Medium: Internet ISSN: 1741-0444 (Electronic) Linking ISSN: 01400118 NLM ISO Abbreviation: Med Biol Eng Comput Subsets: MEDLINE

Výrazy ze slovníku MeSH: Signal Processing, Computer-Assisted*/instrumentation , Data Compression*/methods , Brain*/physiology , Prostheses and Implants*, Algorithms ; Humans ; Signal-To-Noise Ratio ; Equipment Design

Constant-time Algorithms for Minimum Spanning Tree and Related Problems on Processor Array with Reconfigurable Bus Systems.

Autoři: Tien-Tai Pan Shun-Shii Lin

Zdroj: Computer Journal; Mar2002, Vol. 45 Issue 2, p174-186, 13p, 2 Diagrams, 4 Charts

Témata: ALGORITHMS, PROGRAMMABLE array logic, COMPUTER buses, COMPUTER systems, ELECTRONIC data processing

Optimal Speed-Up Parallel Image Template Matching Algorithms on Processor Arrays with a Reconfigurable Bus System

Autoři: Chia-Ho Chen Tzong-Wann Kao Shun-Shan Tsai a další

Zdroj: Computer Vision and Image Understanding. 71:393-412

Témata: 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology

Přístupová URL adresa: https://dblp.uni-trier.de/db/journals/cviu/cviu71.html#TsaiHTLKC98
https://doi.org/10.1006/cviu.1998.0638
https://www.sciencedirect.com/science/article/pii/S1077314298906385
http://www.sciencedirect.com/science/article/pii/S1077314298906385

Parallel hierarchical clustering algorithms on processor arrays with a reconfigurable bus system

Autoři: Tsai, H. R. Horng, S. J. Lee, S. S. a další

Přispěvatelé: Tsai, H. R. Horng, S. J. Lee, S. S. a další

Zdroj: Pattern Recognition. 30:801-815

Témata: bus system, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology

Přístupová URL adresa: https://ui.adsabs.harvard.edu/abs/1997PatRe..30..801H/abstract
https://www.sciencedirect.com/science/article/pii/S0031320396001197
http://www.sciencedirect.com/science/article/pii/S0031320396001197
https://dblp.uni-trier.de/db/journals/pr/pr30.html#TsaiHLTK97

Faulty core recovery mechanisms for a three-dimensional network on a processor array