Výsledky vyhledávání - "partial evaluation implementation technique"

System-level modelling of dynamic reconfigurable designs using functional programming abstractions

Autoři: Jan Kuper Bahram N. Uchevler Kjetil Svarstad a další

Zdroj: International Symposium on Quality Electronic Design (ISQED). :379-385

Témata: IR-87636, 0209 industrial biotechnology, EWI-23903, 02 engineering and technology, Self-Reconfiguration, digital circuit verification, Functional HDL, dynamic reconfigurable designs, functional programming abstractions, 0202 electrical engineering, electronic engineering, information engineering, logic design, high-level descriptions, Suzaku-sz410 board, high-level Haskell descriptions, EC Grant Agreement nr.: FP7/248465, synthesizable VHDL, FPGA Design, Higher-order functions, system-level modelling, Run-Time Reconfiguration, CLaSH tool, Field programmable gate arrays, run-time reconfigurable systems, METIS-302553, high-level structures, Formal verification, Partial Evaluation, RT level, partial evaluation implementation technique, Hardware Description Languages

Přístupová URL adresa: https://research.utwente.nl/en/publications/e0599eaa-a668-4fff-8849-86ec259851c2
https://doi.org/10.1109/ISQED.2013.6523639
https://ieeexplore.ieee.org/document/6523639/
https://research.utwente.nl/en/publications/system-level-modelling-of-dynamic-reconfigurable-designs-using-fu
https://dblp.uni-trier.de/db/conf/isqed/isqed2013.html#UchevlerSKB13