Search Results - "microarchitectural security"
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Authors:
Source: 2025 IEEE Symposium on Security and Privacy (SP)
Subject Terms: systems security, transient execution, hardware security, side channels, spectre, microarchitectural security, program and binary analysis
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Authors: et al.
Contributors: et al.
Source: International Conference on Security and Cryptography (SECRYPT) ; : 22nd International Conference on Security and Cryptography ; https://telecom-paris.hal.science/hal-05097215 ; : 22nd International Conference on Security and Cryptography, Jun 2025, Bilbao, Spain
Subject Terms: Microarchitectural Security Side-Channel Attacks gem5 Simulator Embedded Systems Cache Timing Analysis Security Privacy Complex Systems RISC-V, Microarchitectural Security, Side-Channel Attacks, gem5 Simulator, Embedded Systems, Cache Timing Analysis, Security, Privacy, Complex Systems, RISC-V, [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR]
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Source: Cybersecurity, 9th European Interdisciplinary Cybersecurity Conference, EICC 2025, Rennes, France, June 18–19, 2025, Proceedings ; EICC 2025 (European Interdisciplinary Cybersecurity Conference 2025) ; https://telecom-paris.hal.science/hal-05097207 ; EICC 2025 (European Interdisciplinary Cybersecurity Conference 2025), Jun 2025, Rennes, France. pp.229-235, ⟨10.1007/978-3-031-94855-8_15⟩
Subject Terms: Microarchitectural Security, Side-Channel Attacks, gem5 Simulator, Embedded Systems, Cache Timing Analysis, [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR]
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Source: The 31st IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2025) ; https://telecom-paris.hal.science/hal-05097227 ; The 31st IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2025), Jul 2025, Ischia, Italy
Subject Terms: Side-channel attacks, Fault-based attacks, Machine learning, Gem5, RISC-V, Flush+fault attack, Security, Detection, Vulnerability assessment, Microarchitectural security, Hardware security, Anomaly detection, [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR]
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Authors: et al.
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Source: Prototyping Custom Hardware Performance Counters in gem5 Simulator: A Framework for RISC-V Side-Channel Attack Assessment ; 25th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS 2025) ; https://telecom-paris.hal.science/hal-05097250 ; 25th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS 2025), Jun 2025, Samos, Greece
Subject Terms: RISC-V Architecture, gem5 Simulator, Hardware Performance Counters (HPCs), Embedded Systems, Side-Channel Attacks, Attack Assessment, Microarchitectural Security, Security Evaluation, [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR]
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Authors: et al.
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Source: Twenty-first edition of the HiPEAC summer school (ACACES 2025) ; https://telecom-paris.hal.science/hal-05114092 ; Twenty-first edition of the HiPEAC summer school (ACACES 2025), Jul 2025, Fiuggi, Italy
Subject Terms: RISC-V Architecture, gem5 Simulator, Hardware Performance Counters (HPCs), Embedded Systems, Side-Channel Attacks, Attack Assessment, Microarchitectural Security, [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR]
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Authors: Ainsworth, Sam
Source: Ainsworth, S 2021, GhostMinion: A Strictness-Ordered Cache System for Spectre Mitigation . in MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture . New York, NY, United States, pp. 592-606, 54th IEEE/ACM International Symposium on Microarchitecture, Athens, Greece, 18/10/21 . https://doi.org/10.1145/3466752.3480074
Subject Terms: FOS: Computer and information sciences, Computer Science - Cryptography and Security, caches, Hardware Architecture (cs.AR), 0103 physical sciences, Spectre, 0202 electrical engineering, electronic engineering, information engineering, microarchitectural security, 02 engineering and technology, Computer Science - Hardware Architecture, Cryptography and Security (cs.CR), 01 natural sciences
File Description: application/pdf
Access URL: http://arxiv.org/pdf/2104.05532
http://arxiv.org/abs/2104.05532
https://ui.adsabs.harvard.edu/abs/2021arXiv210405532A/abstract
https://arxiv.org/abs/2104.05532
https://arxiv.org/pdf/2104.05532
https://www.research.ed.ac.uk/en/publications/ghostminion-a-strictness-ordered-cache-system-for-spectre-mitigat
https://dblp.uni-trier.de/db/journals/corr/corr2104.html#abs-2104-05532
https://dl.acm.org/doi/pdf/10.1145/3466752.3480074
https://hdl.handle.net/20.500.11820/9aa9d308-a0d7-4f4a-a439-5d8598a6beef
https://www.pure.ed.ac.uk/ws/files/225838540/GhostMinion_AINSWORTH_DOA14072021_AFV.pdf -
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Authors: Oleksenko, Oleksii
Thesis Advisors: Fetzer, Christof, Bos, Herbert, Technische Universität Dresden
Subject Terms: information security, microarchitectural security, speculative execution, side channel, side-channel attack, microarchitectural defence, computer architecture, spectre, Informationssicherheit, mikroarchitektonische Sicherheit, spekulative Ausführung, Seitenkanal, Seitenkanalangriff, mikroarchitektonische Verteidigung, Computerarchitektur, Spectre, info:eu-repo/classification/ddc/004, ddc:004
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Authors: et al.
Contributors: et al.
Subject Terms: microarchitectural security, microarchitectural side channels, data at rest
File Description: application/pdf
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Authors: et al.
Contributors: et al.
Subject Terms: Computer engineering, Deep Neural Networks, Heterogeneous Systems, Microarchitectural Security, Side-Channels
File Description: PDF; application/pdf
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Authors: et al.
Contributors: et al.
Subject Terms: Cache side-channel attacks, Cache covert-channel attacks, Transient execution attacks, Secure cache defenses, Microarchitectural security, Hardware security, Processor caches, socio, manag
Relation: http://hdl.handle.net/1853/67270
Availability: http://hdl.handle.net/1853/67270
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Authors: et al.
Index Terms: information security, microarchitectural security, speculative execution, side channel, side-channel attack, microarchitectural defence, computer architecture, spectre, Informationssicherheit, mikroarchitektonische Sicherheit, spekulative Ausführung, Seitenkanal, Seitenkanalangriff, mikroarchitektonische Verteidigung, Computerarchitektur, Spectre, info:eu-repo/classification/ddc/004, ddc:004, info:eu-repo/semantics/publishedVersion, doc-type:doctoralThesis, info:eu-repo/semantics/doctoralThesis, doc-type:Text
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