Search Results - "logic locking"

Hybrid Logic Locking Using Horned Lizard Optimization and Q-Learning for Secure Hardware Design

Authors: S., Karthik C., Sujatha M., Premkumar

Source: Tehnicki vjesnik - Technical Gazette. 32

Subject Terms: logic locking, intellectual property protection, hardware security, horned lizard optimization, Q-Learning

File Description: application/pdf

TOP: A Combined Logical and Physical Obfuscation Method for Securing Networks-on-Chip Against Reverse Engineering Attacks

Authors: Mona Hashemi Siamak Mohammadi Trevor E. Carlson

Source: IEEE Access, Vol 13, Pp 133438-133456 (2025)

Subject Terms: logic locking, hardware obfuscation, Electrical engineering. Electronics. Nuclear engineering, Network-on-chip, power-gating, TK1-9971

Access URL: https://doaj.org/article/baa095218772469c9cbd3ae2cd215379

A Survey on AI-Augmented Secure RTL Design for Hardware Trojan Prevention

Authors: Raj Parikh Khushi Parikh

Source: Journal of Computer and Communications. 13:197-209

Subject Terms: Deep Learning in Power Analysis, Jumping-Knowledge GNNs, Siamese Neural Networks (SNNs), Logic Locking, Verilog/VHDL Code Analysis

STATION: State Encoding-Based Attack-Resilient Sequential Obfuscation

Authors: Zhaokun Han Aneesh Dixit Satwik Patnaik et al.

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 43:2888-2901

Subject Terms: IP protection, FSM encoding, Sequential obfuscation, Logic locking, Finite state machine

File Description: application/pdf

NC-ROLL-FIA: Negative capacitance FET based designs for robust logic locking against fault injection attacks enabling trustworthy hardware for edge AI devices

Authors: Kadiyam Tirumalarao Ramesh Vaddi M. Durga Prakash et al.

Source: Results in Engineering, Vol 27, Iss , Pp 106962- (2025)

Subject Terms: Fault injection attack (FIA), Hardware obfuscation, Hardware security, Logic locking, Negative capacitance FETs (NCFETs), Trustworthy edge AI devices, Technology

File Description: electronic resource

Relation: http://www.sciencedirect.com/science/article/pii/S2590123025030191; https://doaj.org/toc/2590-1230

Access URL: https://doaj.org/article/08a9d2d7b55e44b8ba9e5cf357708180

OptiLock: Automated Optimization of Learning-Resilient Logic Locking

Authors: Zeng Wang Lilas Alrahis Animesh Basak Chowdhury et al.

Source: IEEE Access, Vol 13, Pp 166649-166669 (2025)

Subject Terms: Logic locking, simulated annealing, hardware security, IP protection, optimization, machine learning, Electrical engineering. Electronics. Nuclear engineering, TK1-9971

File Description: electronic resource

Relation: https://ieeexplore.ieee.org/document/11174136/; https://doaj.org/toc/2169-3536

Access URL: https://doaj.org/article/2c2070c36b134d3e832d0d541c765b68

Gatelock: input-dependent key-based locked gates for sat resistant logic locking

Authors: Rathor, Vijaypal Singh Singh, Munesh Sahoo, Kshira Sagar et al.

Source: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. 32(2):361-371

Subject Terms: Anti-satisfiability (SAT), Hardware, hardware Trojan, Intellectual property, intellectual property (IP), IP piracy, IP protection, Logic gates, logic locking, Resistance, SAT-attack, Security, Synthetic aperture sonar, Trojan horses

File Description: print

Access URL: https://urn.kb.se/resolve?urn=urn:nbn:se:umu:diva-219534

A survey on AI-augmented Secure RTL design for hardware trojan prevention

Authors: Parikh, Raj Parikh, Khushi

Subject Terms: Logic Locking, Deep Learning in Power Analysis, Siamese Neural Networks (SNNs), Jumping-Knowledge GNNs, Verilog/VHDL Code Analysis

Relation: https://zenodo.org/communities/ijsrarchive/; https://zenodo.org/records/17008141; oai:zenodo.org:17008141; https://doi.org/10.5281/zenodo.17008141

Availability: https://doi.org/10.5281/zenodo.17008141
https://zenodo.org/records/17008141

Protecting Dynamically Obfuscated Scan Chain Architecture from DOSCrack with Trivium Pseudo-Random Number Generation

Authors: Jiaming Wu Olivia Dizon-Paradis Sazadur Rahman et al.

Source: Cryptography ; Volume 9 ; Issue 1 ; Pages: 6

Subject Terms: scan-based attack, clustering, symbolic execution, logic locking

File Description: application/pdf

Relation: Hardware Security; https://dx.doi.org/10.3390/cryptography9010006

Availability: https://doi.org/10.3390/cryptography9010006

Quantum Logic Locking for Security

Authors: Rasit Onur Topaloglu

Source: J, Vol 6, Iss 3, Pp 411-420 (2023)
J; Volume 6; Issue 3; Pages: 411-420

Subject Terms: logic locking, quantum logic locking (QLL), Science, information_technology_data_management, quantum circuit, qubit, quantum computing, quantum security, hardware security

File Description: application/pdf

Access URL: https://doaj.org/article/ee15bce4dc134bc8af7e969faa8255ff

Designing ML-resilient locking at register-transfer level

Authors: Sisejkovic D. Collini L. Tan B. et al.

Source: Proceedings of the 59th ACM/IEEE Design Automation Conference. :769-774

Subject Terms: logic locking, FOS: Computer and information sciences, IP protection, machine learning, Computer Science - Cryptography and Security, RTL, 0202 electrical engineering, electronic engineering, information engineering, deobfuscation, 02 engineering and technology, Cryptography and Security (cs.CR)

File Description: application/pdf

Access URL: http://arxiv.org/abs/2203.05399
https://hdl.handle.net/11311/1227114
https://doi.org/10.1145/3489517.3530541

Quantum Logic Locking for Security

Authors: Rasit Onur Topaloglu

Source: J, Vol 6, Iss 3, Pp 411-420 (2023)

Subject Terms: quantum computing, quantum circuit, qubit, quantum security, quantum logic locking (QLL), logic locking, Science

File Description: electronic resource

Relation: https://www.mdpi.com/2571-8800/6/3/27; https://doaj.org/toc/2571-8800

Access URL: https://doaj.org/article/ee15bce4dc134bc8af7e969faa8255ff

Optimizing the Use of Behavioral Locking for High-Level Synthesis

Authors: Christian Pilato Luca Collini Luca Cassano et al.

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 42:462-472

Subject Terms: FOS: Computer and information sciences, Measurement, Space exploration, Computer Science - Cryptography and Security, Entropy, Integrated circuits, 02 engineering and technology, Foundries, Behavioral sciences, IP Protection, Hardware Architecture (cs.AR), Security, 0202 electrical engineering, electronic engineering, information engineering, Hardware Security, High-Level Synthesis, Computer Science - Hardware Architecture, Cryptography and Security (cs.CR), Logic Locking

File Description: application/pdf

Access URL: http://arxiv.org/abs/2105.09666
https://hdl.handle.net/11311/1227117
https://doi.org/10.1109/TCAD.2022.3179651

ReTrustFSM: Toward RTL Hardware Obfuscation-A Hybrid FSM Approach

Authors: M. Sazadur Rahman Rui Guo Hadi M. Kamali et al.

Source: IEEE Access, Vol 11, Pp 19741-19761 (2023)

Subject Terms: logic locking, FSM, RTL, 0202 electrical engineering, electronic engineering, information engineering, structural analysis, Electrical engineering. Electronics. Nuclear engineering, 02 engineering and technology, BMC, Hardware obfuscation, TK1-9971

Access URL: https://doaj.org/article/c0e35c5763fd48deae6b188a0813f9c5

Power Analysis Attack Against post-SAT Logic Locking schemes

Authors: Riadi, Nassim Bruguier, Florent Benoit, Pascal et al.

Contributors: Riadi, Nassim Bruguier, Florent Benoit, Pascal et al.

Source: ETS 2024 - 29th IEEE European Test Symposium ; https://hal-lirmm.ccsd.cnrs.fr/lirmm-04628663 ; ETS 2024 - 29th IEEE European Test Symposium, May 2024, The Hague, Netherlands. pp.1-6, ⟨10.1109/ETS61313.2024.10567311⟩

Subject Terms: Trust, Logic Locking, Differential Power Analysis, Resistance, Integrated circuits, Electronics industry, Globalization, Europe, Intellectual property, Germanium, Design-for-Trust, [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR], [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, [SPI.TRON]Engineering Sciences [physics]/Electronics

Subject Geographic: The Hague, Netherlands

Availability: https://hal-lirmm.ccsd.cnrs.fr/lirmm-04628663
https://hal-lirmm.ccsd.cnrs.fr/lirmm-04628663v1/document
https://hal-lirmm.ccsd.cnrs.fr/lirmm-04628663v1/file/Power_Analysis_Attack_Against_post-SAT_Logic_Locking_schemes.pdf
https://doi.org/10.1109/ETS61313.2024.10567311

Full key recovery for advanced Logic Locking Schemes

Authors: Riadi, Nassim Bruguier, Florent Flottes, Marie-Lise et al.

Contributors: Riadi, Nassim Bruguier, Florent Flottes, Marie-Lise et al.

Source: CHES 2024 - Conference on Cryptographic Hardware and Embedded Systems ; https://hal-lirmm.ccsd.cnrs.fr/lirmm-04689311 ; CHES 2024 - Conference on Cryptographic Hardware and Embedded Systems, Sep 2024, Halifax, Canada. ; https://ches.iacr.org

Subject Terms: Trust, Logic Locking, Differential Power Analysis, Hardware obfuscation, VLSI Design, [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR], [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, [SPI.TRON]Engineering Sciences [physics]/Electronics

Subject Geographic: Halifax

Time: Halifax, Canada

Availability: https://hal-lirmm.ccsd.cnrs.fr/lirmm-04689311
https://hal-lirmm.ccsd.cnrs.fr/lirmm-04689311v1/document
https://hal-lirmm.ccsd.cnrs.fr/lirmm-04689311v1/file/riadi_nassim_ches_poster.pdf

Logic Locking: Exploration of a new key-gate based on tristate logic

Authors: Dupuis, Sophie Riadi, Nassim Moroukian, Clémy et al.

Contributors: Dupuis, Sophie Riadi, Nassim Moroukian, Clémy et al.

Source: LATS 2024 - 25th IEEE Latin American Test Symposium ; https://hal-lirmm.ccsd.cnrs.fr/lirmm-04564164 ; LATS 2024 - 25th IEEE Latin American Test Symposium, Apr 2024, Maceio, Brazil. pp.1-6, ⟨10.1109/LATS62223.2024.10534598⟩ ; https://cas.polito.it/LATS2024/

Subject Terms: Hardware trust, Design-for-Trust, Logic locking, Tristate logic, Output corruption, SAT attack, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics

Subject Geographic: Brazil

Time: Maceio, Brazil

Availability: https://hal-lirmm.ccsd.cnrs.fr/lirmm-04564164
https://hal-lirmm.ccsd.cnrs.fr/lirmm-04564164v1/document
https://hal-lirmm.ccsd.cnrs.fr/lirmm-04564164v1/file/LATS24_camera_ready_FINAL%20copie%20%281%29.pdf
https://doi.org/10.1109/LATS62223.2024.10534598

Towards a Formal Treatment of Logic Locking

Authors: Peter Beerel Marios Georgiou Ben Hamlin et al.

Source: Transactions on Cryptographic Hardware and Embedded Systems, Vol 2022, Iss 2 (2022)

Subject Terms: TK7885-7895, Computer engineering. Computer hardware, 0202 electrical engineering, electronic engineering, information engineering, Information technology, 02 engineering and technology, T58.5-58.64, Logic Locking, Security Definitions

Access URL: https://tches.iacr.org/index.php/TCHES/article/download/9482/9023
https://doaj.org/article/b54f3872f7404eb993e31159e7e0e222

Logic Locking Using Emerging 2T/3T Magnetic Tunnel Junctions for Hardware Security

Authors: Divyanshu Divyanshu Rajat Kumar Danial Khan et al.

Contributors: Divyanshu Divyanshu Rajat Kumar Danial Khan et al.

Source: IEEE Access, Vol 10, Pp 102386-102395 (2022)

Subject Terms: logic locking, spintronics, magnetic tunnel junction (MTJ), spin-orbit torque (SOT), 0202 electrical engineering, electronic engineering, information engineering, hardware security, Electrical engineering. Electronics. Nuclear engineering, 02 engineering and technology, CMOS technology, TK1-9971

File Description: application/pdf

Access URL: https://doaj.org/article/4c211f57733846448a1516c8de305386

Utilizing layout effects for analog logic locking

Authors: Aljafar, Muayad, J. Azaïs, Florence Flottes, Marie-Lise et al.

Contributors: Aljafar, Muayad, J. Azaïs, Florence Flottes, Marie-Lise et al.

Source: ISSN: 2190-8508.

Subject Terms: Analog obfuscation, Layout-based effects, Logic locking, Hardware security, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics

Availability: https://hal-lirmm.ccsd.cnrs.fr/lirmm-04658699
https://hal-lirmm.ccsd.cnrs.fr/lirmm-04658699v1/document
https://hal-lirmm.ccsd.cnrs.fr/lirmm-04658699v1/file/Analog%20Logic%20Locking.pdf
https://doi.org/10.1007/s13389-024-00350-8