Search Results - "hardware acceleration"
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1
Authors: De Haro Ruiz, Juan Miguel
Contributors: University/Department: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
Thesis Advisors: Álvarez Martínez, Carlos, Jiménez González, Daniel
Source: TDX (Tesis Doctorals en Xarxa)
Subject Terms: High Performance Computing (HPC), Field-Programmable Gate Array (PFGA), task scheduling, task-based programming models, computer architecture, CPU, MPI, High-Level Synthesis (HLS), energy efficiency, programmability, many-core architectures, FPGA clusters, hardware runtimes, hardware acceleration, ASIC, Implicit Message Passing (IMP), Àrees temàtiques de la UPC::Informàtica, 004 - Informàtica
File Description: application/pdf
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2
Authors: et al.
Source: Papadakis, O, Papadimitriou, M, Stratikopoulos, A, Xekalaki, M, Fumero Alfonso, J & Kotselidis, C-E 2025, 'Offloading Key Switching on GPUs : A Path towards Seamless Acceleration of FHE', Paper presented at IEEE International Conference on Cyber Security and Resilience, Chania, Greece, 4/08/25-6/08/25.
Frontiers in Artificial IntelligenceSubject Terms: data privacy, GPUs, hardware acceleration, fully homomorphic encryption
File Description: application/pdf
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3
Authors: et al.
Source: IEEE Access. 12:11850-11864
Subject Terms: BFV, hardware acceleration, homomorphic encryption, number theoretic transform
File Description: print
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4
Authors: et al.
Source: Proceedings of the Great Lakes Symposium on VLSI 2025. :14-21
Subject Terms: Ntt, Seven-Step, Four-Step, Hardware Acceleration, Negacyclic, Fully-Pipelined, Fhe, Fpga
Access URL: https://hdl.handle.net/11772/19360
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5
Authors: et al.
Source: Proceedings of the 22nd ACM International Conference on Computing Frontiers. :84-87
Subject Terms: Hardware Architecture, FOS: Computer and information sciences, AI Hardware Acceleration, Barrier Synchronization, Bulk Synchronous Parallel, Many-core architectures, Massively Parallel systems, Hardware Architecture (cs.AR)
Access URL: http://arxiv.org/abs/2506.11668
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6
Authors: et al.
Source: 2025 IEEE International Symposium on Circuits and Systems (ISCAS). :1-5
Subject Terms: Circuits and systems, Instruction sets, Computer architecture, NIST, Cryptography, Standards, Field programmable gate arrays, Hardware acceleration, Clocks, RISC-V, Core-V eXtension InterFace, Post-Quantum Cryptography, FPGA
File Description: application/pdf
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7
Authors: et al.
Contributors: et al.
Source: 2025 IEEE International Symposium on Circuits and Systems (ISCAS). :1-5
Subject Terms: [INFO.INFO-AI] Computer Science [cs]/Artificial Intelligence [cs.AI], [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], Deep Learning, RF Modulation Recognition, AI Hardware Acceleration, CNN
File Description: application/pdf
Access URL: https://hal.science/hal-04938861v1
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8
Authors: Alex, Anish
Source: World Journal of Advanced Research and Reviews. 26:3809-3816
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9
Authors: Pentaparthi, Sai Kalyan Reddy
Source: World Journal of Advanced Research and Reviews. 26:1485-1492
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10
Authors:
Source: Proceedings of the Twentieth European Conference on Computer Systems. :110-127
Subject Terms: FOS: Computer and information sciences, Computer Science - Machine Learning, Model Inference and Serving, Computer Science - Distributed, Parallel, and Cluster Computing, Quantization, Hardware Acceleration, Machine Learning Systems, Distributed, Parallel, and Cluster Computing (cs.DC), Model Compression, Sparsity, Machine Learning (cs.LG)
Access URL: http://arxiv.org/abs/2312.05215
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11
Authors: et al.
Source: Transactions on Cryptographic Hardware and Embedded Systems, Vol 2025, Iss 2 (2025)
Subject Terms: TK7885-7895, 4604 Cybersecurity and privacy, Computer engineering. Computer hardware, Elliptic Curve Cryptography, Hardware Acceleration, Information technology, T58.5-58.64, Multi-Scalar Multiplication, Zero-Knowledge Proof
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12
Authors: et al.
Source: Transactions on Cryptographic Hardware and Embedded Systems, Vol 2025, Iss 2 (2025)
Subject Terms: TK7885-7895, FOS: Computer and information sciences, Computer engineering. Computer hardware, Computer Science - Cryptography and Security, Hardware Acceleration, CKKS, Information technology, Homomorphic Encryption, Chiplets, T58.5-58.64, Cryptography and Security (cs.CR)
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13
Authors: et al.
Source: IEEE Transactions on Nuclear Science, ISSN 1558-1578, 2025-03-03, Vol. 72, No. 3
Archivo Digital UPM
Universidad Politécnica de MadridSubject Terms: Informática, fieldprogrammable gate array (FPGA), CODAC Core System (CCS), real-time framework (RTF), high-level Synthesis (HLS), Energía Nuclear, hardware acceleration techniques, Electrónica, open computing language (OpenCL)
File Description: application/pdf
Access URL: https://oa.upm.es/89070/
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14
Authors:
Source: IEEE Sensors Journal. 25:7838-7847
Subject Terms: FOS: Computer and information sciences, Hardware acceleration, Computer Vision and Pattern Recognition (cs.CV), Optical flow, Image and Video Processing (eess.IV), Visual odometry, Computer Science - Computer Vision and Pattern Recognition, FOS: Electrical engineering, electronic engineering, information engineering, Electrical Engineering and Systems Science - Image and Video Processing
Access URL: http://arxiv.org/abs/2406.13345
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15
Authors:
Source: IEEE Access, Vol 13, Pp 70282-70297 (2025)
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16
Authors: et al.
Source: IEEE Access, Vol 13, Pp 44636-44649 (2025)
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17
Authors:
Source: IEEE Access, Vol 13, Pp 87862-87883 (2025)
IEEE Access -
18
Authors:
Source: IEEE Access, Vol 13, Pp 67821-67855 (2025)
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19
Source: Jisuanji gongcheng, Vol 51, Iss 9, Pp 71-79 (2025)
Subject Terms: winograd, convolutional acceleration operator, hardware acceleration, heterogeneous sampling, field programmable gate array (fpga), Computer engineering. Computer hardware, TK7885-7895, Computer software, QA76.75-76.765
File Description: electronic resource
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20
Authors: Andrade, João Rodrigo Pinheiro Faria
Subject Terms: Code generation, FPGAs, Hardware acceleration, High level synthesis, Neural networks
File Description: application/pdf
Availability: http://hdl.handle.net/10773/45886
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