Search Results - "hardware acceleration"

Accelerating many-core, heterogeneous, and distributed architectures with hardware runtimes and programming models

Authors: De Haro Ruiz, Juan Miguel

Contributors: University/Department: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors

Thesis Advisors: Álvarez Martínez, Carlos, Jiménez González, Daniel

Source: TDX (Tesis Doctorals en Xarxa)

Subject Terms: High Performance Computing (HPC), Field-Programmable Gate Array (PFGA), task scheduling, task-based programming models, computer architecture, CPU, MPI, High-Level Synthesis (HLS), energy efficiency, programmability, many-core architectures, FPGA clusters, hardware runtimes, hardware acceleration, ASIC, Implicit Message Passing (IMP), Àrees temàtiques de la UPC::Informàtica, 004 - Informàtica

File Description: application/pdf

Access URL: http://hdl.handle.net/10803/695347
https://dx.doi.org/10.5821/dissertation-2117-442722

Offloading Key Switching on GPUs: A Path towards Seamless Acceleration of FHE: A Path towards Seamless Acceleration of FHE

Authors: Papadakis, Orion Papadimitriou, Michail Stratikopoulos, Athanasios et al.

Source: Papadakis, O, Papadimitriou, M, Stratikopoulos, A, Xekalaki, M, Fumero Alfonso, J & Kotselidis, C-E 2025, 'Offloading Key Switching on GPUs : A Path towards Seamless Acceleration of FHE', Paper presented at IEEE International Conference on Cyber Security and Resilience, Chania, Greece, 4/08/25-6/08/25.
Frontiers in Artificial Intelligence

Subject Terms: data privacy, GPUs, hardware acceleration, fully homomorphic encryption

File Description: application/pdf

Access URL: https://research.manchester.ac.uk/en/publications/8fb46b07-97ff-4576-a4e5-df18792f26b3
https://pure.manchester.ac.uk/ws/files/478022428/paper.pdf
https://research.manchester.ac.uk/en/publications/8fb46b07-97ff-4576-a4e5-df18792f26b3

Heterogeneous Reconfigurable Accelerator for Homomorphic Evaluation on Encrypted Data

Authors: Song, Wenqing Shen, Sirui Xu, Congwei et al.

Source: IEEE Access. 12:11850-11864

Subject Terms: BFV, hardware acceleration, homomorphic encryption, number theoretic transform

File Description: print

Access URL: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-343900
https://doi.org/10.1109/ACCESS.2024.3354275

IO-Optimized Design-Time Configurable Negacyclic Seven-Step NTT Architecture for FHE Applications

Authors: Emre Kocer Selim Kirbiyik Tolun Tosun et al.

Source: Proceedings of the Great Lakes Symposium on VLSI 2025. :14-21

Subject Terms: Ntt, Seven-Step, Four-Step, Hardware Acceleration, Negacyclic, Fully-Pipelined, Fhe, Fpga

Access URL: https://hdl.handle.net/11772/19360

FractalSync: Lightweight Scalable Global Synchronization of Massive Bulk Synchronous Parallel AI Accelerators

Authors: Victor Isachi Alessandro Nadalini Riccardo Fiorani Gallotta et al.

Source: Proceedings of the 22nd ACM International Conference on Computing Frontiers. :84-87

Subject Terms: Hardware Architecture, FOS: Computer and information sciences, AI Hardware Acceleration, Barrier Synchronization, Bulk Synchronous Parallel, Many-core architectures, Massively Parallel systems, Hardware Architecture (cs.AR)

Access URL: http://arxiv.org/abs/2506.11668

RISC-V Based Keccak Co-Processor for NIST Post-Quantum Cryptography Standards

Authors: Dolmeta, Alessandra Piscopo, Valeria Mirigaldi, Mattia et al.

Source: 2025 IEEE International Symposium on Circuits and Systems (ISCAS). :1-5

Subject Terms: Circuits and systems, Instruction sets, Computer architecture, NIST, Cryptography, Standards, Field programmable gate arrays, Hardware acceleration, Clocks, RISC-V, Core-V eXtension InterFace, Post-Quantum Cryptography, FPGA

File Description: application/pdf

Access URL: https://ieeexplore.ieee.org/document/11043433
https://hdl.handle.net/11583/3001803
https://doi.org/10.1109/iscas56072.2025.11043433

A Power-Efficient Attention-Infused CNN Hardware Accelerator for RF Spectrum Monitoring

Authors: Song, Zhifan Emad Abdelazim, Abdelrahman Bazargan-Sabet, Pirouz et al.

Contributors: Song, Zhifan Emad Abdelazim, Abdelrahman Bazargan-Sabet, Pirouz et al.

Source: 2025 IEEE International Symposium on Circuits and Systems (ISCAS). :1-5

Subject Terms: [INFO.INFO-AI] Computer Science [cs]/Artificial Intelligence [cs.AI], [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], Deep Learning, RF Modulation Recognition, AI Hardware Acceleration, CNN

File Description: application/pdf

Access URL: https://hal.science/hal-04938861v1

Specialized cloud hardware for AI workloads: Current state and future directions

Authors: Alex, Anish

Source: World Journal of Advanced Research and Reviews. 26:3809-3816

Subject Terms: Neuromorphic Computing, AI Infrastructure, Hardware Acceleration, Photonic Computing, Distributed Training

Optimizing generative AI models for edge deployment: Techniques and best practices

Authors: Pentaparthi, Sai Kalyan Reddy

Source: World Journal of Advanced Research and Reviews. 26:1485-1492

Subject Terms: Generative AI, Quantization, Neural Architecture Search, Edge Computing, Hardware Acceleration, Model Compression

DeltaZip: Efficient Serving of Multiple Full-Model-Tuned LLMs

Authors: Xiaozhe Yao Qinghao Hu Ana Klimovic

Source: Proceedings of the Twentieth European Conference on Computer Systems. :110-127

Subject Terms: FOS: Computer and information sciences, Computer Science - Machine Learning, Model Inference and Serving, Computer Science - Distributed, Parallel, and Cluster Computing, Quantization, Hardware Acceleration, Machine Learning Systems, Distributed, Parallel, and Cluster Computing (cs.DC), Model Compression, Sparsity, Machine Learning (cs.LG)

Access URL: http://arxiv.org/abs/2312.05215

OPTIMSM: FPGA hardware accelerator for Zero-Knowledge MSM

Authors: Pottier, Xander de Ruijter, Thomas Bertels, Jonas et al.

Source: Transactions on Cryptographic Hardware and Embedded Systems, Vol 2025, Iss 2 (2025)

Subject Terms: TK7885-7895, 4604 Cybersecurity and privacy, Computer engineering. Computer hardware, Elliptic Curve Cryptography, Hardware Acceleration, Information technology, T58.5-58.64, Multi-Scalar Multiplication, Zero-Knowledge Proof

Access URL: https://doaj.org/article/6e426054ceaf48098f846f91c7df0b6e
https://lirias.kuleuven.be/handle/20.500.12942/754729

REED: Chiplet-based Accelerator for Fully Homomorphic Encryption

Authors: Aikata Aikata Ahmet Can Mert Sunmin Kwon et al.

Source: Transactions on Cryptographic Hardware and Embedded Systems, Vol 2025, Iss 2 (2025)

Subject Terms: TK7885-7895, FOS: Computer and information sciences, Computer engineering. Computer hardware, Computer Science - Cryptography and Security, Hardware Acceleration, CKKS, Information technology, Homomorphic Encryption, Chiplets, T58.5-58.64, Cryptography and Security (cs.CR)

Access URL: https://ches.iacr.org/2025/papersubmission.php
http://arxiv.org/abs/2308.02885
https://doaj.org/article/34753f156de344aa888202a3394a148d

Integration of Hardware Acceleration Techniques in a Real-Time Framework Using FPGA Devices

Authors: González Brito, César Ruiz González, Mariano Nieto Valhondo, Julián et al.

Source: IEEE Transactions on Nuclear Science, ISSN 1558-1578, 2025-03-03, Vol. 72, No. 3
Archivo Digital UPM
Universidad Politécnica de Madrid

Subject Terms: Informática, fieldprogrammable gate array (FPGA), CODAC Core System (CCS), real-time framework (RTF), high-level Synthesis (HLS), Energía Nuclear, hardware acceleration techniques, Electrónica, open computing language (OpenCL)

File Description: application/pdf

Access URL: https://oa.upm.es/89070/

Low Latency Visual Inertial Odometry With On-Sensor Accelerated Optical Flow for Resource-Constrained UAVs

Authors: Jonas Kühne Michele Magno Luca Benini

Source: IEEE Sensors Journal. 25:7838-7847

Subject Terms: FOS: Computer and information sciences, Hardware acceleration, Computer Vision and Pattern Recognition (cs.CV), Optical flow, Image and Video Processing (eess.IV), Visual odometry, Computer Science - Computer Vision and Pattern Recognition, FOS: Electrical engineering, electronic engineering, information engineering, Electrical Engineering and Systems Science - Image and Video Processing

Access URL: http://arxiv.org/abs/2406.13345

FPGA Acceleration With Hessian-Based Comprehensive Intra-Layer Mixed-Precision Quantization for Transformer Models

Authors: Woohong Byun Jongseok Woo Saibal Mukhopadhyay

Source: IEEE Access, Vol 13, Pp 70282-70297 (2025)

Subject Terms: hardware acceleration, Hessian, Accelerator, activation, Electrical engineering. Electronics. Nuclear engineering, FPGA, BERT, TK1-9971

Access URL: https://doaj.org/article/da9ffb2491b54cb28451692fa6253c77

Accelerating Euclidean Distance Transforms: A Fast and Flexible Approach With Multi-Vendor GPU, Multi-Threading, and Multi-Language Support

Authors: Dale Black Wenbo Li Qiyu Zhang et al.

Source: IEEE Access, Vol 13, Pp 44636-44649 (2025)

Subject Terms: high performance computing, Distance transform, Hausdorff distance, hardware acceleration, Electrical engineering. Electronics. Nuclear engineering, medical image analysis, image processing, TK1-9971

Access URL: https://doaj.org/article/b70f0fc6d932475aa1819e2ff327db14

High-Performance Number Theoretic Transform on GPU Through radix2-CT and 4-Step Algorithms

Authors: Alisah Ozcan Arsalan Javeed Erkay Savas

Source: IEEE Access, Vol 13, Pp 87862-87883 (2025)
IEEE Access

Subject Terms: Graphical processing unit, hardware acceleration, homomorphic cryptography, Electrical engineering. Electronics. Nuclear engineering, polynomial arithmetic, number theoretic transform, TK1-9971

Access URL: https://doaj.org/article/9bd77f00aa4f4a54bf6df257b4991058

Privacy-Preserving Deep Learning: A Survey on Theoretical Foundations, Software Frameworks, and Hardware Accelerators

Authors: Eric Jahns Milan Stojkov Michel A. Kinsy

Source: IEEE Access, Vol 13, Pp 67821-67855 (2025)

Subject Terms: federated learning, differential privacy, hardware acceleration, homomorphic encryption, Deep learning, Electrical engineering. Electronics. Nuclear engineering, multi-party computation, TK1-9971

Access URL: https://doaj.org/article/ab62444de9294f7bbdf6965fc619203b

Winograd Heterogeneous Sampling Window Convolution Acceleration Operator

Authors: PENG Yun, WANG Yubing, LIANG Lei, SONG Yue, QIU Cheng, LEI Yuxin, JIA Peng, MIAO Guoqing, QIN Li, WANG Lijun

Source: Jisuanji gongcheng, Vol 51, Iss 9, Pp 71-79 (2025)

Subject Terms: winograd, convolutional acceleration operator, hardware acceleration, heterogeneous sampling, field programmable gate array (fpga), Computer engineering. Computer hardware, TK7885-7895, Computer software, QA76.75-76.765

File Description: electronic resource

Relation: https://www.ecice06.com/fileup/1000-3428/PDF/jsjgc-51-9-71.pdf; https://doaj.org/toc/1000-3428

Access URL: https://doaj.org/article/5e79342851bd4480b43cab83b002f74e

High-level synthesis-oriented automatic code generation for FPGA acceleration of neural networks

Authors: Andrade, João Rodrigo Pinheiro Faria

Subject Terms: Code generation, FPGAs, Hardware acceleration, High level synthesis, Neural networks

File Description: application/pdf

Availability: http://hdl.handle.net/10773/45886