Výsledky vyhledávání - "field-programmable gate array implementations"

Optimized Sequential State Encoding Methods for Finite-State Machines in Field-Programmable Gate Array Implementations

Autoři: Valery Salauyou Witali Bułatow

Zdroj: Applied Sciences, Vol 14, Iss 13, p 5594 (2024)

Témata: finite-state machine (FSM), state encoding, sequential encoding method, field-programmable gate array (FPGA), area, performance, Technology, Engineering (General). Civil engineering (General), TA1-2040, Biology (General), QH301-705.5, Physics, QC1-999, Chemistry, QD1-999

Popis souboru: electronic resource

Relation: https://www.mdpi.com/2076-3417/14/13/5594; https://doaj.org/toc/2076-3417

Přístupová URL adresa: https://doaj.org/article/5f7d18d5d46a4447a3b427d20edfdd74

Digital signal processor against field programmable gate array implementations of space–code correlator beamformer for smart antennas

Autoři: DİNÇER, HASAN TANGEL, ALİ ŞAHİN, SALİH a další

Zdroj: IET Microwaves, Antennas & Propagation. 4:593-599

Témata: 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, 7. Clean energy

Přístupová URL adresa: https://digital-library.theiet.org/content/journals/10.1049/iet-map.2009.0151
https://www.infona.pl/resource/bwmeta1.element.ieee-art-000005463064
http://akademikpersonel.kocaeli.edu.tr/hdincer/sci/hdincer20.03.2011_22.27.05sci.pdf
https://ieeexplore.ieee.org/document/5463064/
http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000005463064
https://avesis.kocaeli.edu.tr/publication/details/4db15e58-0919-4147-a996-669789b8ef2d/oai
https://avesis.yeniyuzyil.edu.tr/publication/details/4db15e58-0919-4147-a996-669789b8ef2d/oai

Density Encoding Enables Resource-Efficient Randomly Connected Neural Networks

Autoři: Kleyko, Denis Kheffache, Mansour Frady, E Paxon a další

Zdroj: IEEE Transactions on Neural Networks and Learning Systems. 32(8):3777-3783

Témata: Density-based encoding, hyperdimensional computing, random vector functional link (RVFL) networks, Encoding (symbols), Field programmable gate arrays (FPGA), Learning algorithms, Machine learning, Network coding, Stochastic systems, Classification tasks, Computationally efficient, Field-programmable gate array implementations, Functional links, Hidden neurons, Resource-efficient, Stochastic computing, UCI machine learning repository, Neural networks

Popis souboru: print

Přístupová URL adresa: https://urn.kb.se/resolve?urn=urn:nbn:se:ri:diva-55946

System for synthesizing field programmable gate array implementations from high level circuit descriptions

Method and apparatus for converting field-programmable gate array implementations into mask-programmable logic cell implementations

A field-programmable gate array implementation of a real-time nonlinear Runge–Kutta model predictive control

Autoři: İplikçi, Serdar. Bahtiyar, B.

Zdroj: Transactions of the Institute of Measurement and Control. 38:555-564

Témata: 0209 industrial biotechnology, model predictive control, Embedded systems, Field programmable gate arrays (FPGA), Signal receivers, 02 engineering and technology, Discrete-time model, Electromagnetic levitation system, Nonlinear continuous-time systems, Predictive control systems, optimal control, Nonlinear control systems, Nonlinear systems, 0202 electrical engineering, electronic engineering, information engineering, Discrete time control systems, Model predictive control, field-programmable gate arrays, Nonlinear model predictive control, Optimal controls, Continuous time systems, Logic gates, Reconfigurable hardware, Electromagnetic propulsion, Runge Kutta methods, Nonlinear model based control, Field-programmable gate array implementations, embedded systems, Small time constants

Přístupová URL adresa: https://journals.sagepub.com/doi/abs/10.1177/0142331215589805
https://hdl.handle.net/11499/10186
https://doi.org/10.1177/0142331215589805
http://acikerisim.pau.edu.tr:8080/xmlui/handle/11499/10186

Digital signal processor against field programmable gate array implementations of space–code correlator beamformer for smart antennas.

Autoři: Dikmese, S. Kavak, A. Kucuk, K. a další

Zdroj: IET Microwaves, Antennas & Propagation (Institution of Engineering & Technology); May2010, Vol. 4 Issue 5, p593-599, 7p, 3 Diagrams, 3 Charts

Témata: DIGITAL signal processing, ANTENNAS (Electronics), FIELD programmable gate arrays, PROGRAMMABLE logic devices, GATE array circuits

Hardware Architectures for Computing Eigendecomposition-Based Discrete Fractional Fourier Transforms with Reduced Arithmetic Complexity.

Autoři: Bispo, Breno C. de Oliveira Neto, José R. Lima, Juliano B.

Zdroj: Circuits, Systems & Signal Processing; Jan2024, Vol. 43 Issue 1, p593-614, 22p

Témata: DISCRETE Fourier transforms, IMAGE encryption, ARITHMETIC, FIELD programmable gate arrays, GATE array circuits

OneBitPitch (OBP): Ultra-High-Speed Pitch Detection Algorithm Based on One-Bit Quantization and Modified Autocorrelation.

Autoři: Coccoluto, Davide Cesarini, Valerio Costantini, Giovanni

Zdroj: Applied Sciences (2076-3417); Jul2023, Vol. 13 Issue 14, p8191, 20p

Témata: GATE array circuits, ALGORITHMS

Hardware architecture of Dillon's APN permutation for different primitive polynomials

Autoři: Imaña Pascual, José Luis Kaleyski, Nikolay Budaghyan, Lilya

Témata: 004.056.55, Almost perfect nonlinear (APN), Block cypher, S-box, Primitive polynomial, Hardware architecture, Seguridad informática, 3304 Tecnología de Los Ordenadores, journal article, VoR

URL: https://hdl.handle.net/20.500.14352/88720
PID2021- 123041OB-I00
S2018/TCS-4423
Construction of Optimal Boolean Functions
314395

Systolic array design space exploration of interpolators for multi‐rate systems.

Autoři: Shoukry, Mohammed Gebali, Fayez Agathoklis, Panajotis

Zdroj: IET Circuits, Devices & Systems (Wiley-Blackwell); Oct2019, Vol. 13 Issue 7, p1032-1038, 7p

Automatic Software and Computing Hardware Codesign for Predictive Control.

Autoři: Khusainov, Bulat Kerrigan, Eric C. Constantinides, George A.

Zdroj: IEEE Transactions on Control Systems Technology; Sep2019, Vol. 27 Issue 5, p2295-2304, 10p

Témata: COMPUTER software

Neural-Network Decoders for Quantum Error Correction Using Surface Codes: A Space Exploration of the Hardware Cost-Performance Tradeoffs

Autoři: Overwater, R.W.J. (author) Babaie, M. (author) Sebastiano, F. (author)

Témata: Qubit, Decoding, Codes, Hardware, Quantum computing, Logic gates, Artificial neural networks, Application-specific integrated circuit (ASIC), complementary metal-oxide semiconductor (CMOS), CMOS integrated circuits, combinational circuits, cryo-CMOS decoding, cryogenic electronics, digital integrated circuits, error correction codes, feedforward neural networks (NNs), field programmable gate array (FPGA), fixed-point arithmetic, machine learning, NNs, pareto analysis, quantum computing, quantum-error-correction (QEC) codes, supervised learning, surface codes (SCs), journal article

URL: http://resolver.tudelft.nl/uuid:d939d34e-8dbd-43ad-b100-655a2931c3bf
http://www.scopus.com/inward/record.url?scp=85131653183&partnerID=8YFLogxK
http://www.scopus.com/inward/record.url?scp=85131653183&partnerID=8YFLogxK
IEEE Transactions on Quantum Engineering--2689-1808--a4dd05f1-fb5d-4459-aa96-33c2df1d9db3

Transforming Group Codes in Mealy Finite State Machines with Composite State Codes.

Autoři: Barkalov, Alexander Titarenko, Larysa Mielcarek, Kamil

Zdroj: Applied Sciences (2076-3417); Apr2025, Vol. 15 Issue 8, p4289, 21p

Témata: FINITE state machines, GATE array circuits, GENERATING functions, LOGIC

Improving Temporal Characteristics of Mealy FSM with Composite State Codes.

Autoři: Barkalov, Alexander Titarenko, Larysa Krzywicki, Kazimierz a další

Zdroj: Electronics (2079-9292); Apr2025, Vol. 14 Issue 7, p1406, 24p

Témata: FINITE state machines, GATE array circuits, GENERATING functions, CONSUMPTION (Economics), LOGIC

Reliable Hardware Architectures of the CORDIC Algorithm With a Fixed Angle of Rotations.

Autoři: Ramadoss, Rajkumar Mozaffari Kermani, Mehran Azarderakhsh, Reza

Zdroj: IEEE Transactions on Circuits & Systems. Part II: Express Briefs; Aug2017, Vol. 64 Issue 8, p972-976, 5p

GPU-Based Gigabit LDPC Decoder.

Autoři: Keskin, Selcuk Kocak, Taskin

Zdroj: IEEE Communications Letters; Aug2017, Vol. 21 Issue 8, p1703-1706, 4p

High-Performance Digital Devices Design by the ASMD-FSMD Technique for Implementation in FPGA.

Autoři: Salauyou, Valery Klimowicz, Adam Grzes, Tomasz

Zdroj: Applied Sciences (2076-3417); Jan2025, Vol. 15 Issue 1, p410, 18p

Témata: FINITE state machines, DIGITAL technology, DESIGN techniques, DIGITAL electronics, CYCLONES

An Asynchronous Recurrent Network of Cellular Automaton-Based Neurons and Its Reproduction of Spiking Neural Network Activities.

Autoři: Matsubara, Takashi Torikai, Hiroyuki

Zdroj: IEEE Transactions on Neural Networks & Learning Systems; Apr2016, Vol. 27 Issue 4, p836-852, 17p

Témata: ARTIFICIAL neural networks, CELLULAR automata, PARALLEL processing, SEQUENTIAL circuits, DIGITAL electronics

New Implementations of the WG Stream Cipher.

Autoři: El-Razouk, Hayssam Reyhani-Masoleh, Arash Gong, Guang

Zdroj: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Sep2014, Vol. 22 Issue 9, p1865-1878, 14p

Témata: SHIFT registers, STREAM ciphers, LOGIC circuits, NORMAL basis theorem, HARDWARE