Suchergebnisse - "decoder implementation"

Ultra-high-throughput EMS NB-LDPC decoder with full-parallel node processing

Autoren: Harb, Hassan Chamas Al Ghouwayel, Ali Conde-Canencia, Laura et al.

Weitere Verfasser: Harb, Hassan Chamas Al Ghouwayel, Ali Conde-Canencia, Laura et al.

Quelle: https://hal.science/hal-02494736 ; 2020.

Schlagwörter: Index Terms-Channel coding, decoder implementation, ASIC, non-binary LDPC, Min-Sum, parity check, [SPI.TRON]Engineering Sciences [physics]/Electronics

Verfügbarkeit: https://hal.science/hal-02494736
https://hal.science/hal-02494736v2/document
https://hal.science/hal-02494736v2/file/TCAS_I_high_throughput_architectures.pdf

A DSP based H.264/SVCdecoder for a multimedia terminal

Autoren: Pescador, Fernando Samper, David Raulet, Mickaël et al.

Weitere Verfasser: Pescador, Fernando Samper, David Raulet, Mickaël et al.

Quelle: IEEE Transactions on Consumer Electronics. 57:705-712

Schlagwörter: decoding, optimisation, scalable video coding, digital signal processing chips, quality of experience, 02 engineering and technology, performance optimization, CIF sequence, 03 medical and health sciences, performance optimizations, 0302 clinical medicine, PC-based decoder, 0202 electrical engineering, electronic engineering, information engineering, multimedia systems, DSP based video decoder, DSP, PC-based decoder implementation, video decoder, multimedia communication, multimedia terminal, video coding, H.264/SVC decoder, CIF sequences, [INFO.INFO-ES] Computer Science [cs]/Embedded Systems, code standards, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, H.26 standard

Dateibeschreibung: application/pdf

Zugangs-URL: http://hal.inria.fr/docs/00/71/74/85/PDF/icce11_1.9.pdf
https://hal.archives-ouvertes.fr/hal-00717325/file/ICCE11_v0.7c.pdf
https://hal.science/hal-00717485v1/document
https://hal.science/hal-00717485v1
https://doi.org/10.1109/tce.2011.5955211
https://hal.science/hal-00717325v1/document
https://doi.org/10.1109/icce.2011.5722651
https://hal.science/hal-00717325v1
https://hal-univ-rennes1.archives-ouvertes.fr/hal-00717325
http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000005955211
https://hal.archives-ouvertes.fr/hal-00717325
https://dblp.uni-trier.de/db/journals/tce/tce57.html#PescadorJRS11
https://doi.org/10.1109/TCE.2011.5955211
https://hal.archives-ouvertes.fr/hal-00717485/document
http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000005722651

A DSP based H.264/SVC decoder for a multimedia terminal

Autoren: Pescador, Fernando Samper, David Raulet, Mickaël et al.

Weitere Verfasser: Pescador, Fernando Samper, David Raulet, Mickaël et al.

Quelle: Consumer Electronics (ICCE), 2011 IEEE International Conference on ; https://hal.science/hal-00717325 ; Consumer Electronics (ICCE), 2011 IEEE International Conference on, Jan 2011, Las Vegas, United States. pp.401 -402, ⟨10.1109/ICCE.2011.5722651⟩

Schlagwörter: CIF sequence, DSP, H.264/SVC decoder, PC-based decoder implementation, multimedia terminal, performance optimization, video decoder, decoding, digital signal processing chips, multimedia systems, optimisation, video coding, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Geographisches Schlagwort: Las Vegas, United States

Verfügbarkeit: https://hal.science/hal-00717325
https://hal.science/hal-00717325/document
https://hal.science/hal-00717325/file/ICCE11_v0.7c.pdf
https://doi.org/10.1109/ICCE.2011.5722651

Ultra-High-Throughput EMS NB-LDPC Decoder with Full-Parallel Node Processing

Autoren: Harb, Hassan Al Ghouwayel, Ali Chamas Conde-Canencia, Laura et al.

Quelle: WoS

Schlagwörter: Computer Science, Information Systems, Engineering, Electrical & Electronic, channel coding, decoder implementation, asic, non-binary ldpc, min-sum, parity check, low-complexity, nonbinary, codes, architecture, design

Relation: https://infoscience.epfl.ch/record/295506/files/s11265-022-01795-y.pdf; Journal Of Signal Processing Systems For Signal Image And Video Technology; https://infoscience.epfl.ch/handle/20.500.14299/189602; WOS:000828958200001

Verfügbarkeit: https://doi.org/10.1007/s11265-022-01795-y
https://infoscience.epfl.ch/handle/20.500.14299/189602
https://hdl.handle.net/20.500.14299/189602

Systolic VLSI Arrays for Polynomial GCD Computation: Systolic VLSI arrays for polynomial GCD computation

Autoren: Hsiang-Tsung Kung Richard P. Brent

Quelle: IEEE Transactions on Computers. :731-736

Schlagwörter: greatest common divisor, polynomials, Decoding, systolic arrays, 0202 electrical engineering, electronic engineering, information engineering, special-purpose hardware, 02 engineering and technology, Symbolic computation and algebraic computation, algorithms, Circuits, networks, Algorithms in computer science, decoder implementation, Polynomials over finite fields

Dateibeschreibung: application/xml

Zugangs-URL: https://ieeexplore.ieee.org/document/5009358/
https://doi.org/10.1109/TC.1984.5009358
http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000005009358
https://dblp.uni-trier.de/db/journals/tc/tc33.html#BrentK84
http://ieeexplore.ieee.org/document/5009358/
https://www.computer.org/csdl/trans/tc/1984/08/05009358.pdf

On-the-fly decoder for multiple byte errors

Autoren: Arvind M. Patel

Quelle: IBM Journal of Research and Development. 30:259-269

Schlagwörter: decoding procedure, LSI chip design, decoder architecture, Reed-Solomon codes, correction of multiple burst errors in binary data, Decoding, Switching theory, application of Boolean algebra, Boolean functions, multiple-error correction, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, BCH codes, decoder implementation, on-the-fly error correction of multiple byte errors

Dateibeschreibung: application/xml

Zugangs-URL: https://zbmath.org/3997700
https://doi.org/10.1147/rd.303.0259
https://dblp.uni-trier.de/db/journals/ibmrd/ibmrd30.html#Patel86
http://ieeexplore.ieee.org/document/5390175/

Pipeline processing in low-density parity-check codes hardware decoder

Autoren: Sułek, W.

Quelle: Bulletin of the Polish Academy of Sciences. Technical Sciences.

Schlagwörter: channel coding, LDPC codes, iterative decoding, decoder implementation, pipelined processing

Zugangs-URL: http://yadda.icm.edu.pl/baztech/element/bwmeta1.element.baztech-article-BPG8-0048-0049

Annular Barcodes

Autoren: Stamm, Christoph

Schlagwörter: Annular Barcodes, Circular Barcodes, generic design, barcode decoder implementation, OpenCV, 600 - Technik

Dateibeschreibung: application/pdf

Relation: IMVS Fokus Report; https://hdl.handle.net/11654/17880

Verfügbarkeit: https://hdl.handle.net/11654/17880
https://doi.org/10.26041/fhnw-644

Custom Datapaths for DSP ASICs Methodology and Implementation

Autoren: Åström, Pontus

Schlagwörter: Electrical Engineering, Electronic Engineering, Information Engineering, Elektroteknik, handshake circuits, design patterns, design abstraction, design methodology, UMTS, interleaver architecture, Turbo decoder implementation, low power, Digital filter, wave digital filter

Relation: https://lup.lub.lu.se/record/465826

Verfügbarkeit: https://lup.lub.lu.se/record/465826