Suchergebnisse - "Verilog/VHDL Code Analysis"

A Survey on AI-Augmented Secure RTL Design for Hardware Trojan Prevention

Autoren: Raj Parikh Khushi Parikh

Quelle: Journal of Computer and Communications. 13:197-209

Schlagwörter: Deep Learning in Power Analysis, Jumping-Knowledge GNNs, Siamese Neural Networks (SNNs), Logic Locking, Verilog/VHDL Code Analysis

A survey on AI-augmented Secure RTL design for hardware trojan prevention

Autoren: Parikh, Raj Parikh, Khushi

Schlagwörter: Logic Locking, Deep Learning in Power Analysis, Siamese Neural Networks (SNNs), Jumping-Knowledge GNNs, Verilog/VHDL Code Analysis

Relation: https://zenodo.org/communities/ijsrarchive/; https://zenodo.org/records/17008141; oai:zenodo.org:17008141; https://doi.org/10.5281/zenodo.17008141

Verfügbarkeit: https://doi.org/10.5281/zenodo.17008141
https://zenodo.org/records/17008141