Výsledky vyhľadávania - "Types and Design Styles—gate arrays General Terms"
-
1
Autori: a ďalší
Prispievatelia: a ďalší
Predmety: Categories and Subject Descriptors, B.6.3 [Logic Design, Design Aids—Optimization, B.7.1 [Integrated Circuits, Types and Design Styles—Gate arrays General Terms, Algorithms, Performance, Design, Experimentation Additional Key Words and Phrases, FPGA, technology mapping, cut enumeration, area flow, edge flow
Popis súboru: application/pdf
Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.152.127; http://www.eecs.berkeley.edu/~alanmi/publications/2009/trets09_wmap.pdf
-
2
Autori: a ďalší
Prispievatelia: a ďalší
Predmety: Categories and Subject Descriptors B.6.3 [Logic Design, Design Aids – Optimization, B.7.1 [Integrated Circuits, Types and Design Styles – Gate arrays General Terms Algorithms, Performance, Design, Experimentation Keywords FPGA, Technology Mapping, Cut Enumeration, Area Flow, Edge Flow
Popis súboru: application/pdf
Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.299.5175; http://www.eecs.berkeley.edu/~alanmi/publications/2008/fpga08_wmap.pdf
-
3
Autori: a ďalší
Prispievatelia: a ďalší
Predmety: Categories and Subject Descriptors B.7.1 [Integrated Circuits, Types and Design Styles – Gate Arrays General Terms, Design. Keywords Field-Programmable Gate Arrays, Power Minimization
Popis súboru: application/pdf
-
4
Autori: a ďalší
Prispievatelia: a ďalší
Predmety: Categories and Subject Descriptors, D.3.4 [Programming Languages, Processors—Code generation, Compilers, Optimization, C.1.3 [Processor Architectures, Other Architecture Styles—Adaptable architectures, B.7.1 [Integrated Circuits, Types and Design Styles—Gate arrays General Terms, Algorithms, Languages, Performance Additional Key Words and Phrases, Instr
Popis súboru: application/pdf
Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.81.6354; http://ce.et.tudelft.nl/publicationfiles/1140_7_MoscuTecs.pdf
-
5
Autori: a ďalší
Prispievatelia: a ďalší
Predmety: Categories and Subject Descriptors, B.6.3 [Logic Design, Design Aides—Automatic synthesis, Optimization, Verification, B.7.1 [Integrated Circuits, Types and Design Styles—Gate arrays General Terms, Design, Verification Additional Key Words and Phrases, Satisfiability
Popis súboru: application/pdf
-
6
Prispievatelia: The Pennsylvania State University CiteSeerX Archives
Predmety: Categories and Subject Descriptors B.7.2 [Integrated Circuits, Design Aids – layout, placement and routing, verification B.7.1 [Integrated Circuits, Types and Design Styles – gate arrays General Terms Design, Verification Keywords FPGA, PLD, programmable logic, automatic layout
Popis súboru: application/pdf
Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.65.1411; http://www.eecg.toronto.edu/~jayar/pubs/kuon/kuonfpga05.pdf
-
7
Autori:
Prispievatelia:
Zdroj: http://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/2004/glsvlsi04/pdffiles/p348.pdf.
Predmety: Categories and Subject Descriptors B.6.3 [Logic Design, Design Aids—Optimization, B.7.1 [Integrated Circuits, Types and Design Styles—Gate Arrays General Terms Algorithms, Design Keywords SPFD, Logic Optimization, One-to-Many Rewiring (OMR
Popis súboru: application/pdf
-
8
Autori: a ďalší
Prispievatelia: a ďalší
Predmety: Categories and Subject Descriptors B.7.1 [Integrated Circuits, Types and Design Styles – Gate Arrays General Terms, Design. Keywords Field-Programmable Gate Arrays, Power Minimization
Popis súboru: application/pdf
Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.553.5284; http://www.ece.ubc.ca/~julienl/papers/pdf/fpga07.pdf
-
9
Autori:
Prispievatelia:
Predmety: Categories and Subject Descriptors, A.1 [Introductory and Survey, B.6.1 [Logic Design, Design Style—logic arrays, B.6.3 [Logic Design, Design Aids, B.7.1 [Integrated Circuits, Types and Design Styles—gate arrays General Terms, Design, Performance Additional Key Words and Phrases, Automatic design, field-programmable, FPGA, manual design
Popis súboru: application/pdf
Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.476.7584; http://www.idi.ntnu.no/emner/tdt22/2011/reconfig.pdf
-
10
Autori:
Prispievatelia:
Predmety: Categories and Subject Descriptors D.3.2 [Programming Languages, Language Classifications–Functional Language, D.3.4 [Programming Languages, Processors–compilers, B.7 [Integrated Circuits, Types and Design Styles–gate arrays General Terms Languages Keywords Functional programming, reconfigurable hardware, FPGA, Hume, VHDL
Popis súboru: application/pdf
Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.308.7758; http://www.macs.hw.ac.uk/~greg/publications/sm.fhpc12.pdf
-
11
Autori: a ďalší
Prispievatelia: a ďalší
Predmety: Categories and Subject Descriptors, B.6.3 [Logic Design, Design Aids—Optimization, B.7.1 [Integrated Circuits, Types and Design Styles—Gate arrays General Terms, Algorithms, Performance, Design, Experimentation Additional Key Words and Phrases, FPGA, don’t-cares, resynthesis, Boolean satisfiability ACM Reference Format
Popis súboru: application/pdf
Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.299.6358; http://www.eecs.berkeley.edu/~alanmi/publications/2011/trets11_mfs.pdf
Nájsť tento článok vo Web of Science