Suchergebnisse - "Types and Design Styles—Gate arrays"
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Schlagwörter: Categories and Subject Descriptors B.3.2 [Memory Structures, Design Styles—Associative Memories, B.7.1 [Integrated Circuits, Types and Design Styles—Gate Arrays, E.2 [Data, Data Storage Representations—Hash-table representations General Terms Algorithms, Design, Performance Keywords FPGA, BRAM, Associative Memory, CAM, Cache, Hashing
Dateibeschreibung: application/pdf
Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.366.3876; http://ic.ese.upenn.edu/pdf/dmhc_fpga2013.pdf
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Autoren: et al.
Weitere Verfasser: et al.
Schlagwörter: Categories and Subject Descriptors B.7.1 [Hardware, Types and Design Styles-Gate Arrays, C.5.0 [Computer Systems Organization, Computer System
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Autoren: et al.
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Schlagwörter: Categories and Subject Descriptors, B.6.3 [Logic Design, Design Aids—Optimization, B.7.1 [Integrated Circuits, Types and Design Styles—Gate arrays General Terms, Algorithms, Performance, Design, Experimentation Additional Key Words and Phrases, FPGA, technology mapping, cut enumeration, area flow, edge flow
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Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.152.127; http://www.eecs.berkeley.edu/~alanmi/publications/2009/trets09_wmap.pdf
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Schlagwörter: Categories and Subject Descriptors, B.7.1 [Integrated Circuits, Types and Design Styles—Gate arrays, B.7.2 [Integrated Circuits, Design Aids—Placement and routing General Terms, Algorithms, Design, Experimentation Additional Key Words and Phrases, FPGA, clock distribution networks, clock-aware placement, low-power design ACM Reference Format
Dateibeschreibung: application/pdf
Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.628.3331; http://www.ece.ubc.ca/~julienl/papers/pdf/trets08.pdf
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Autoren: et al.
Weitere Verfasser: et al.
Schlagwörter: Categories and Subject Descriptors B.6.3 [Logic Design, Design Aids – Optimization, B.7.1 [Integrated Circuits, Types and Design Styles – Gate arrays General Terms Algorithms, Performance, Design, Experimentation Keywords FPGA, Technology Mapping, Cut Enumeration, Area Flow, Edge Flow
Dateibeschreibung: application/pdf
Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.299.5175; http://www.eecs.berkeley.edu/~alanmi/publications/2008/fpga08_wmap.pdf
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Schlagwörter: B.7.1 [Integrated Circuits, Types and Design Styles— Gate arrays, I.6.5 [Simulation and Modeling, Model
Dateibeschreibung: application/pdf
Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.152.1456; http://www.eecg.toronto.edu/~jayar/pubs/fang/fangfpga08.pdf
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Autoren: et al.
Weitere Verfasser: et al.
Schlagwörter: Categories and Subject Descriptors B.7.1 [Integrated Circuits, Types and Design Styles – Gate Arrays General Terms, Design. Keywords Field-Programmable Gate Arrays, Power Minimization
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Autoren: et al.
Weitere Verfasser: et al.
Schlagwörter: Categories and Subject Descriptors, D.3.4 [Programming Languages, Processors—Code generation, Compilers, Optimization, C.1.3 [Processor Architectures, Other Architecture Styles—Adaptable architectures, B.7.1 [Integrated Circuits, Types and Design Styles—Gate arrays General Terms, Algorithms, Languages, Performance Additional Key Words and Phrases, Instr
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Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.81.6354; http://ce.et.tudelft.nl/publicationfiles/1140_7_MoscuTecs.pdf
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Autoren: et al.
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Schlagwörter: Categories and Subject Descriptors B.7.1 [Integrated Circuits, Types and Design Styles— Gate arrays, C.1 [Processor Architectures, Miscellaneous General Terms Design, Performance Keywords FPGA, Reconfigurable processor, Technology scaling
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Autoren: et al.
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Quelle: http://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/2004/fpga04/pdffiles/p200.pdf.
Schlagwörter: Categories and Subject Descriptors B.7.1 [Integrated Circuits, Types and Design Styles| Gate arrays, C.1 [Processor Architectures, Miscella- neous General Terms Design, Performance Keywords FPGA, Recongurable processor, Technology scaling
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Autoren: et al.
Weitere Verfasser: et al.
Quelle: http://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/2004/fpga04/pdffiles/p099.pdf.
Schlagwörter: Categories and Subject Descriptors B.6.3 [Logic Design, Design Aids – Automatic synthesis, Optimization, B.7.1 [Integrated Circuits, Types and Design Styles – Gate arrays, B.7.2 [Integrated Circuits, Design Aids – Layout, Placement and routing, B.8.2 [Performance and Reliability, Performance Analysis and Design Aids. General Terms Algorithms, Performance, Design. Keywords FPGA, Logic synthesis, Placement, Timing Optimization
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Autoren: et al.
Weitere Verfasser: et al.
Schlagwörter: Categories and Subject Descriptors, B.6.3 [Logic Design, Design Aides—Automatic synthesis, Optimization, Verification, B.7.1 [Integrated Circuits, Types and Design Styles—Gate arrays General Terms, Design, Verification Additional Key Words and Phrases, Satisfiability
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Autoren: et al.
Weitere Verfasser: et al.
Schlagwörter: Categories and Subject Descriptors, B.6.3 [Logic Design, Design Aids—Optimization, B.7.1 [Integrated Circuits, Types and Design Styles—Gate arrays, J.6 [Computer-Aided Engineering, Computer-aided design (CAD) General Terms, Algorithms Additional Key Words and Phrases, Delay minimization, FPGA, power optimization, technology
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Autoren: et al.
Weitere Verfasser: et al.
Schlagwörter: Categories and Subject Descriptors B.7.1 [Integrated Circuits, Types and Design Styles— Gate arrays, C.5.3 [Computer System Implementation, Microcomputers—Microprocessors General Terms Design, Performance Keywords FPGA, Reconfigurable processor, Pipeline, Energy
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Schlagwörter: Categories and Subject Descriptors, B.7.1 [Integrated Circuits, Types and Design Styles— Gate arrays, B.7.2 [Integrated Circuits, Design aids—Placement and routing, J.6 [Computer Applications, Computer-Aided Engineering General Terms, Algorithms, Design, Experimentation, Measurement, Performance Additional Key Words and Phrases, Computer-aided design of VLSI, field-programmable gate arrays
Dateibeschreibung: application/pdf
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Autoren:
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Schlagwörter: Categories and Subject Descriptors, B.7.1 [Integrated Circuits, Types and Design Styles--- Gate arrays, B.7.2 [Integrated Circuits, Design aids---Placement and routing, J.6 [Computer Applications, Computer-Aided Engineering General Terms, Algorithms, Design, Experimentation, Measurement, Performance Additional Key Words and Phrases, Computer-aided design of VLSI, field-programmable gate arrays, layout, synthesis
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Autoren: et al.
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Schlagwörter: Categories and Subject Descriptors, B.7.1 [Integrated Circuits, Types and Design Styles—Gate arrays, B.7.2 [Integrated Circuits, Design Aids—Placement and routing, J.6 [Computer Applications, Computer-Aided Engineering General Terms, Algorithms, Design, Experimentation, Measurement, Performance Additional Key Words and Phrases, Computer-aided design of VLSI, dynamically reconfigurable, layout
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Autoren: et al.
Weitere Verfasser: et al.
Schlagwörter: Categories and Subject Descriptors, B.7.1 [Integrated Circuits, Types and Design Styles— Gate arrays, B.7.2 [Integrated Circuits, Design Aids—Placement and routing, J.6 [Computer Applications, Computer-Aided Engineering General Terms, Algorithms, Design, Experimentation, Measurement, Performance Additional Key Words and Phrases, Computer-aided design of VLSI, field-programmable gate array, layout, synthesis
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Autoren: et al.
Weitere Verfasser: et al.
Schlagwörter: Categories and Subject Descriptors, B.7.1 [Integrated Circuits, Types and Design Styles— gate arrays, B.7.2 [Integrated Circuits, Design Aids—placement and routing General Terms, Design, Experimentation, Measurement, Performance, Theory, Verification
Dateibeschreibung: application/pdf
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Schlagwörter: Categories and Subject Descriptors, B.6.1 [Logic Design, Design Styles—combinational logic, B.6.3 [Logic Design, Design Aids—automatic synthesis, optimization, B.7.1 [Integrated Circuits, Types and Design Styles—gate arrays, J.6 [Computer-Aided Engineering, Computer-Aided Design General Terms, Algorithms, Design, Experimentation, Measurement, Performance, Theory Additional Key Words and Phrases, Area minimization, computer-aided design of VLSI, decomposition, delay minimization, delay modeling, FPGA, logic optimization, power minimi
Dateibeschreibung: application/pdf
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