Search Results - "Types AND Design Styles – algorithm implementation in hardware"

Data Reorganization Engines for the Next Generation of System-On-a-Chip FPGAs*

Authors: Pedro C. Diniz Joonseok Park The Pennsylvania State University CiteSeerX Archives

Contributors: Pedro C. Diniz Joonseok Park The Pennsylvania State University CiteSeerX Archives

Source: http://www.sigda.org/Archives/ProceedingArchives/Fpga/Fpga2002/papers/2002/fpga02/pdffiles/8_3.pdf.

Subject Terms: Categories and Subject Descriptors B.5.1 [Register-Transfer-Level Implementation, Design Aids – automatic synthesis, B.7.1 [Integrated Circuits, Types and Design Styles – algorithm implementation in hardware, B.6.2 [Logic Design, Design Styles – memory control and access, D.3.4 [Programming Languages, Processors – compilers. Keywords Data Reorganization, High-level Synthesis, Field-Programmable- Gate-Arrays (FPGAs

File Description: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.108.1615; http://www.sigda.org/Archives/ProceedingArchives/Fpga/Fpga2002/papers/2002/fpga02/pdffiles/8_3.pdf

Availability: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.108.1615
http://www.sigda.org/Archives/ProceedingArchives/Fpga/Fpga2002/papers/2002/fpga02/pdffiles/8_3.pdf