Výsledky vyhledávání - "Types AND Design Styles—gate arrays General Terms"
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Témata: Categories and Subject Descriptors, B.6.3 [Logic Design, Design Aids—Optimization, B.7.1 [Integrated Circuits, Types and Design Styles—Gate arrays General Terms, Algorithms, Performance, Design, Experimentation Additional Key Words and Phrases, FPGA, technology mapping, cut enumeration, area flow, edge flow
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Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.152.127; http://www.eecs.berkeley.edu/~alanmi/publications/2009/trets09_wmap.pdf
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Témata: Categories and Subject Descriptors B.6.3 [Logic Design, Design Aids – Optimization, B.7.1 [Integrated Circuits, Types and Design Styles – Gate arrays General Terms Algorithms, Performance, Design, Experimentation Keywords FPGA, Technology Mapping, Cut Enumeration, Area Flow, Edge Flow
Popis souboru: application/pdf
Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.299.5175; http://www.eecs.berkeley.edu/~alanmi/publications/2008/fpga08_wmap.pdf
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Témata: Categories and Subject Descriptors B.7.1 [Integrated Circuits, Types and Design Styles – Gate Arrays General Terms, Design. Keywords Field-Programmable Gate Arrays, Power Minimization
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Témata: Categories and Subject Descriptors, D.3.4 [Programming Languages, Processors—Code generation, Compilers, Optimization, C.1.3 [Processor Architectures, Other Architecture Styles—Adaptable architectures, B.7.1 [Integrated Circuits, Types and Design Styles—Gate arrays General Terms, Algorithms, Languages, Performance Additional Key Words and Phrases, Instr
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Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.81.6354; http://ce.et.tudelft.nl/publicationfiles/1140_7_MoscuTecs.pdf
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Témata: Categories and Subject Descriptors, B.6.3 [Logic Design, Design Aides—Automatic synthesis, Optimization, Verification, B.7.1 [Integrated Circuits, Types and Design Styles—Gate arrays General Terms, Design, Verification Additional Key Words and Phrases, Satisfiability
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Přispěvatelé: The Pennsylvania State University CiteSeerX Archives
Témata: Categories and Subject Descriptors B.7.2 [Integrated Circuits, Design Aids – layout, placement and routing, verification B.7.1 [Integrated Circuits, Types and Design Styles – gate arrays General Terms Design, Verification Keywords FPGA, PLD, programmable logic, automatic layout
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Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.65.1411; http://www.eecg.toronto.edu/~jayar/pubs/kuon/kuonfpga05.pdf
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Zdroj: http://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/2004/glsvlsi04/pdffiles/p348.pdf.
Témata: Categories and Subject Descriptors B.6.3 [Logic Design, Design Aids—Optimization, B.7.1 [Integrated Circuits, Types and Design Styles—Gate Arrays General Terms Algorithms, Design Keywords SPFD, Logic Optimization, One-to-Many Rewiring (OMR
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Témata: Categories and Subject Descriptors B.7.1 [Integrated Circuits, Types and Design Styles – Gate Arrays General Terms, Design. Keywords Field-Programmable Gate Arrays, Power Minimization
Popis souboru: application/pdf
Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.553.5284; http://www.ece.ubc.ca/~julienl/papers/pdf/fpga07.pdf
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Témata: Categories and Subject Descriptors, A.1 [Introductory and Survey, B.6.1 [Logic Design, Design Style—logic arrays, B.6.3 [Logic Design, Design Aids, B.7.1 [Integrated Circuits, Types and Design Styles—gate arrays General Terms, Design, Performance Additional Key Words and Phrases, Automatic design, field-programmable, FPGA, manual design
Popis souboru: application/pdf
Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.476.7584; http://www.idi.ntnu.no/emner/tdt22/2011/reconfig.pdf
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Témata: Categories and Subject Descriptors D.3.2 [Programming Languages, Language Classifications–Functional Language, D.3.4 [Programming Languages, Processors–compilers, B.7 [Integrated Circuits, Types and Design Styles–gate arrays General Terms Languages Keywords Functional programming, reconfigurable hardware, FPGA, Hume, VHDL
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Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.308.7758; http://www.macs.hw.ac.uk/~greg/publications/sm.fhpc12.pdf
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Témata: Categories and Subject Descriptors, B.6.3 [Logic Design, Design Aids—Optimization, B.7.1 [Integrated Circuits, Types and Design Styles—Gate arrays General Terms, Algorithms, Performance, Design, Experimentation Additional Key Words and Phrases, FPGA, don’t-cares, resynthesis, Boolean satisfiability ACM Reference Format
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Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.299.6358; http://www.eecs.berkeley.edu/~alanmi/publications/2011/trets11_mfs.pdf
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Zdroj: DAC: Annual ACM/IEEE Design Automation Conference; Jun2011, p818-823, 6p, 2 Diagrams, 5 Charts
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Zdroj: 2010 ACM/IEEE International Symposium on Low-Power Electronics & Design (ISLPED); 2010, p55-60, 6p
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Zdroj: DAC: Annual ACM/IEEE Design Automation Conference; 2008, p120-125, 6p, 3 Color Photographs, 8 Diagrams, 4 Charts
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Zdroj: Proceedings 41st Design Automation Conference, 2004; 2004, p874-877, 4p
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Zdroj: Proceedings 41st Design Automation Conference, 2004; 2004, p198-203, 6p
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Zdroj: ACM Transactions on Embedded Computing Systems; Aug2012, Vol. 11, p1-25, 25p
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