Suchergebnisse - "Task based programming models"

Accelerating many-core, heterogeneous, and distributed architectures with hardware runtimes and programming models

Autoren: De Haro Ruiz, Juan Miguel

Weitere Verfasser: University/Department: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors

Thesis Advisors: Álvarez Martínez, Carlos, Jiménez González, Daniel

Quelle: TDX (Tesis Doctorals en Xarxa)

Schlagwörter: High Performance Computing (HPC), Field-Programmable Gate Array (PFGA), task scheduling, task-based programming models, computer architecture, CPU, MPI, High-Level Synthesis (HLS), energy efficiency, programmability, many-core architectures, FPGA clusters, hardware runtimes, hardware acceleration, ASIC, Implicit Message Passing (IMP), Àrees temàtiques de la UPC::Informàtica, 004 - Informàtica

Dateibeschreibung: application/pdf

Zugangs-URL: http://hdl.handle.net/10803/695347
https://dx.doi.org/10.5821/dissertation-2117-442722

ALPI: Enhancing portability and interoperability of task-aware libraries

Autoren: Sala Penadés, Kevin Álvarez Robert, David Peñacoba Veigas, Raúl et al.

Weitere Verfasser: Sala Penadés, Kevin Álvarez Robert, David Peñacoba Veigas, Raúl et al.

Schlagwörter: Àrees temàtiques de la UPC::Informàtica::Programació, Parallel programming (Computer science), Computer software -- Development, Task-based programming models, Runtime systems, OpenMP, OmpSs-2, Portability, Interoperability, Programació en paral·lel (Informàtica), Programari -- Desenvolupament

Dateibeschreibung: 12 p.; application/pdf

Relation: https://link.springer.com/chapter/10.1007/978-3-031-61763-8_14; info:eu-repo/grantAgreement/AEI//CEX2021-001148-S; info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/PID2019-107255GB-C21/ES/BSC - COMPUTACION DE ALTAS PRESTACIONES VIII/; https://hdl.handle.net/2117/409813

Verfügbarkeit: https://hdl.handle.net/2117/409813
https://doi.org/10.1007/978-3-031-61763-8_14

Storage-Heterogeneity Aware Task-based Programming Models to Optimize I/O Intensive Applications

Autoren: Hatem Elshazly Jorge Ejarque Rosa M. Badia et al.

Weitere Verfasser: Hatem Elshazly Jorge Ejarque Rosa M. Badia et al.

Quelle: UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)

Schlagwörter: Task-based programming models, Ordinadors -- Memòries, Resource pooling, Heterogeneous storage systems, I/O scheduling, Checkpointing, Heterogeneity abstraction, 02 engineering and technology, Computer storage devices, Task scheduling, Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, 0202 electrical engineering, electronic engineering, information engineering, Automatic data movement, I/O intensive applications, Informàtica::Arquitectura de computadors [Àrees temàtiques de la UPC]

Dateibeschreibung: application/pdf

Zugangs-URL: https://hdl.handle.net/2117/367747
https://doi.org/10.1109/tpds.2022.3161123

DDS: integrating data analytics transformations in task-based workflows [version 2; peer review: 1 approved, 2 approved with reservations]

Autoren: Rosa M. Badia Javier Alvarez Jorge Ejarque et al.

Quelle: Open Research Europe, Vol 2 (2023)

Schlagwörter: Big Data High Performance, Data Analytics, Parallel Computing, Task Based Programming Models, eng, Science, Social Sciences

Dateibeschreibung: electronic resource

Relation: https://open-research-europe.ec.europa.eu/articles/2-66/v2; https://doaj.org/toc/2732-5121

Zugangs-URL: https://doaj.org/article/828c00dc8e224da3be72d91b81ad4851

A Linux Kernel Scheduler Extension for Multi-core Systems

Autoren: Roca Nonell, Aleix Rodríguez, Samuel Segura, Albert et al.

Weitere Verfasser: Roca Nonell, Aleix Rodríguez, Samuel Segura, Albert et al.

Quelle: UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
2019 IEEE 26th International Conference on High Performance Computing, Data, and Analytics (HiPC)

Schlagwörter: FOS: Computer and information sciences, Task-based programming models, I/O, Operating Systems (cs.OS), D.4.1, D.3.3, Multiprocessadors, 02 engineering and technology, Linux kernel, Computer Science - Operating Systems, multi-core, Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, Computer Science - Distributed, Parallel, and Cluster Computing, [INFO.INFO-OS] Computer Science [cs]/Operating Systems [cs.OS], HPC, 0202 electrical engineering, electronic engineering, information engineering, Multiprocessors, Superordinadors, scheduling, High performance computing, Distributed, Parallel, and Cluster Computing (cs.DC), Linux kernel scheduler, Informàtica::Arquitectura de computadors [Àrees temàtiques de la UPC]

Dateibeschreibung: application/pdf

Zugangs-URL: http://arxiv.org/pdf/2004.06354
http://arxiv.org/abs/2004.06354
https://inria.hal.science/hal-02410082v1

TACL: Interoperating asynchronous device APIs with task-based programming models

Autoren: Alvarez, David Sala Penadés, Kevin Beltran, Vicenç

Schlagwörter: Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, High performance computing, Task-based Programming Models, OmpSS-2, Heterogeneous Computing, High-Performance Computing, Càlcul intensiu (Informàtica)

Dateibeschreibung: 2 p.; application/pdf

Relation: http://hdl.handle.net/2117/381039

Verfügbarkeit: http://hdl.handle.net/2117/381039

DDS: integrating data analytics transformations in task-based workflows [version 1; peer review: 1 approved, 2 approved with reservations]

Autoren: Rosa M. Badia Javier Alvarez Jorge Ejarque et al.

Quelle: Open Research Europe, Vol 2 (2022)

Schlagwörter: Big Data High Performance, Data Analytics, Parallel Computing, Task Based Programming Models, eng, Science, Social Sciences

Dateibeschreibung: electronic resource

Relation: https://open-research-europe.ec.europa.eu/articles/2-66/v1; https://doaj.org/toc/2732-5121

Zugangs-URL: https://doaj.org/article/64fe5bd34d6a4e19ab6b0d841f96f1c8

A Hardware Runtime for Task-Based Programming Models

Autoren: Xubin Tan Jaume Bosch Carlos Alvarez et al.

Weitere Verfasser: Xubin Tan Jaume Bosch Carlos Alvarez et al.

Quelle: UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
instname

Schlagwörter: Heterogeneous task scheduling, Matrius de portes programables per l'usuari, Parallel processing (Electronic computers), Task-based programming models, Processament en paral·lel (Ordinadors), Field programmable gate arrays, Multiprocessadors, 02 engineering and technology, Fine-grained parallelism, Nested tasks, Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles, Energy saving, 0202 electrical engineering, electronic engineering, information engineering, Multiprocessors, Task-dependence analysis, Informàtica::Arquitectura de computadors::Arquitectures paral·leles [Àrees temàtiques de la UPC], FPGA

Dateibeschreibung: application/pdf

Zugangs-URL: https://upcommons.upc.edu/bitstream/2117/173031/1/A%20Hardware%20Runtime%20for%20Task-based.pdf
http://hdl.handle.net/2117/173031
https://hdl.handle.net/2117/173031
https://doi.org/10.1109/tpds.2019.2907493

Applying StarPU runtime system to scientific applications: Experiences and lessons learned

Autoren: Tzanos, Georgios Soni, Vineet Prouveur, Charles et al.

Weitere Verfasser: Tzanos, Georgios Soni, Vineet Prouveur, Charles et al.

Quelle: POMCO 2020 - 2nd International Workshop on Parallel Optimization using/for Multi- and Many-core High Performance Computing ; https://inria.hal.science/hal-02985721 ; POMCO 2020 - 2nd International Workshop on Parallel Optimization using/for Multi- and Many-core High Performance Computing, Dec 2020, Barcelona / Virtual, Spain

Schlagwörter: HPC, task-based programming models, StarPU, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

Geographisches Schlagwort: Spain

Time: Barcelona / Virtual, Spain

Relation: info:eu-repo/grantAgreement//801015/EU/Enhancing Programmability and boosting Performance Portability for Exascale Computing Systems/EXA2PRO

Verfügbarkeit: https://inria.hal.science/hal-02985721
https://inria.hal.science/hal-02985721v1/document
https://inria.hal.science/hal-02985721v1/file/POMCO2020-camera-ready.pdf

Design and implementation of an architecture-aware hardware runtime for heterogeneous systems

Autoren: De Haro Ruiz, Juan Miguel Bosch Pons, Jaume Jiménez González, Daniel

Schlagwörter: Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, High performance computing, heterogeneous systems, task-dependence analysis, High-performance computing, FPGA, task-based programming models, Càlcul intensiu (Informàtica)

Dateibeschreibung: 2 p.; application/pdf; application/rdf+xml; charset=utf-8

Relation: https://hdl.handle.net/2117/331025

Verfügbarkeit: https://hdl.handle.net/2117/331025

Reducing Cache Coherence Traffic with a NUMA-Aware Runtime Approach

Autoren: Caheny, Paul Álvarez Martí, Lluc Derradji, Said et al.

Weitere Verfasser: Caheny, Paul Álvarez Martí, Lluc Derradji, Said et al.

Quelle: UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
instname
IEEE Transactions on Parallel and Distributed Systems

Schlagwörter: Parallel processing (Electronic computers), Task-based programming models, Processament en paral·lel (Ordinadors), Gestió de memòria (Informàtica), 02 engineering and technology, 01 natural sciences, NUMA, Memory management (Computer science), Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Cache coherence, Informàtica::Arquitectura de computadors [Àrees temàtiques de la UPC]

Dateibeschreibung: application/pdf

Zugangs-URL: https://upcommons.upc.edu/bitstream/2117/116365/3/Reducing%2bCache%2bCoherence%2bTraffic%2bwith%2ba.pdf
http://hdl.handle.net/2117/116365
https://hdl.handle.net/2117/116365
https://doi.org/10.1109/tpds.2017.2787123

OmpSs@FPGA framework for high performance FPGA computing

Autoren: De Haro Ruiz, Juan Miguel Bosch Pons, Jaume Filgueras Izquierdo, Antonio et al.

Weitere Verfasser: De Haro Ruiz, Juan Miguel Bosch Pons, Jaume Filgueras Izquierdo, Antonio et al.

Schlagwörter: Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles, Field programmable gate arrays, Parallel processing (Electronic computers), Compilers (Computer programs), FPGA, Reconfigurable hardware, Parallel architectures, Task-based programming models, High-level synthesis, Matrius de portes programables per l'usuari, Processament en paral·lel (Ordinadors), Compiladors (Programes d'ordinador)

Dateibeschreibung: 14 p.; application/pdf

Relation: https://ieeexplore.ieee.org/document/9445632; info:eu-repo/grantAgreement/EC/H2020/754337/EU/Co-designed Innovation and System for Resilient Exascale Computing in Europe: From Applications to Silicon/EuroEXA; info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/PID2019-107255GB-C22/ES/UPC-COMPUTACION DE ALTAS PRESTACIONES VIII/; info:eu-repo/grantAgreement/AGAUR/2017 SGR 1414; info:eu-repo/grantAgreement/AGAUR/2017-SGR-1328; https://hdl.handle.net/2117/347629

Verfügbarkeit: https://hdl.handle.net/2117/347629
https://doi.org/10.1109/TC.2021.3086106

Reducing Cache Coherence Traffic with Hierarchical Directory Cache and NUMA-Aware Runtime Scheduling

Autoren: Caheny, Paul Casas, Marc Moretó Planas, Miquel et al.

Weitere Verfasser: Caheny, Paul Casas, Marc Moretó Planas, Miquel et al.

Quelle: UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
instname
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation-PACT 16
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation-PACT '16
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation

Schlagwörter: NUMA, Memory management (Computer science), Task-based programming models, Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, Cache memory, 0103 physical sciences, Memòria ràpida de treball (Informàtica), Memòria cau, Gestió de memòria (Informàtica), Cache coherence, Informàtica::Arquitectura de computadors [Àrees temàtiques de la UPC], 01 natural sciences

Dateibeschreibung: application/pdf

Zugangs-URL: http://hdl.handle.net/2117/96470
https://hdl.handle.net/2117/96470
https://doi.org/10.1145/2967938.2967962

Introducing the Task-Aware Storage I/O (TASIO) Library

Autoren: Roca Nonell, Aleix Beltran Querol, Vicenç Mateo Bellido, Sergi et al.

Weitere Verfasser: Roca Nonell, Aleix Beltran Querol, Vicenç Mateo Bellido, Sergi et al.

Schlagwörter: Àrees temàtiques de la UPC::Enginyeria electrònica, High performance computing, Task-Based Programming Models, I/O, OmpSs-2, OpenMP, HPC, Supercomputadors

Dateibeschreibung: 15 p.; application/pdf

Relation: https://link.springer.com/chapter/10.1007/978-3-030-28596-8_19; info:eu-repo/grantAgreement/EC/H2020/754304/EU/DEEP/DEEP-EST; info:eu-repo/grantAgreement/MINECO//TIN2015-65316-P/ES/COMPUTACION DE ALTAS PRESTACIONES VII/; http://hdl.handle.net/2117/168271

Verfügbarkeit: http://hdl.handle.net/2117/168271
https://doi.org/10.1007/978-3-030-28596-8_19

Adaptive Runtime-Assisted Block Prefetching on Chip-Multiprocessors

Autoren: García Flores, Víctor Rico Carro, Alejandro Villavieja Prados, Carlos et al.

Weitere Verfasser: García Flores, Víctor Rico Carro, Alejandro Villavieja Prados, Carlos et al.

Quelle: UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
instname

Schlagwörter: Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, Cache memory, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Memòria cau, Gestió de memòria (Informàtica), Task based programming models, 02 engineering and technology, Cache memories, Prefetch, Informàtica::Arquitectura de computadors [Àrees temàtiques de la UPC], 01 natural sciences

Dateibeschreibung: application/pdf

Zugangs-URL: https://upcommons.upc.edu/bitstream/2117/100924/1/IJPP-full-manuscript.pdf
http://hdl.handle.net/2117/100924

PARSECSs: Evaluating the Impact of Task Parallelism in the PARSEC Benchmark Suite

Autoren: Chasapis, Dimitrios Casas, Marc Moretó Planas, Miquel et al.

Weitere Verfasser: Chasapis, Dimitrios Casas, Marc Moretó Planas, Miquel et al.

Quelle: Recercat. Dipósit de la Recerca de Catalunya
instname
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)

Schlagwörter: 2. Zero hunger, Task-based programming models, 4. Education, 1. No poverty, Parallel programming (Computer science), 02 engineering and technology, Synchronization, Programació en paral·lel (Informàtica), Parallel applications, Parallel benchmarks, Parallel architectures, Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, Scalable applications, Concurrency, 0202 electrical engineering, electronic engineering, information engineering, Informàtica::Arquitectura de computadors [Àrees temàtiques de la UPC], Parallel runtime systems

Dateibeschreibung: application/pdf

Zugangs-URL: https://dl.acm.org/doi/pdf/10.1145/2829952?download=true
http://hdl.handle.net/2117/88472
https://hdl.handle.net/2117/88472
https://doi.org/10.1145/2829952

Optimizing Locality by Topology-aware Placement for a Task Based Programming Model

Autoren: Gustedt, Jens Jeannot, Emmanuel Mansouri, Farouk et al.

Weitere Verfasser: Gustedt, Jens Jeannot, Emmanuel Mansouri, Farouk et al.

Quelle: IEEE Cluster 2016 Conference ; https://hal.science/hal-01416284 ; IEEE Cluster 2016 Conference, Sep 2016, Taipei, Taiwan. , pp.164 - 165, ⟨10.1109/CLUSTER.2016.87⟩ ; http://ieeecluster2016.org/

Schlagwörter: Threads affinity, Task-based programming models, Parallelism, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing

Geographisches Schlagwort: Taipei, Taiwan

Verfügbarkeit: https://hal.science/hal-01416284
https://hal.science/hal-01416284v1/document
https://hal.science/hal-01416284v1/file/bare_conf_2pages.pdf
https://doi.org/10.1109/CLUSTER.2016.87

Runtime-guided management of scratchpad memories in multicore architectures

Autoren: Álvarez Martí, Lluc Moretó Planas, Miquel Casas, Marc et al.

Weitere Verfasser: Álvarez Martí, Lluc Moretó Planas, Miquel Casas, Marc et al.

Schlagwörter: Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, Cache memory, Multiprocessors, Scratchpad memories, Task-based programming models, Memòria cau, Multiprocessadors

Dateibeschreibung: 13 p.; application/pdf

Relation: http://dx.doi.org/10.1109/PACT.2015.26; http://hdl.handle.net/2117/88597

Verfügbarkeit: http://hdl.handle.net/2117/88597
https://doi.org/10.1109/PACT.2015.26

RADAR: Runtime-Assisted Dead Region Management for Last-Level Caches

Autoren: Manivannan, Madhavan Papaefstathiou, Vasileios Pericas, Miquel et al.

Schlagwörter: last level cache, task-based programming models, runtime system, dead block prediction

Zugangs-URL: https://research.chalmers.se/publication/218513

On the application task granularity and the interplay with the scheduling overhead in many-core shared memory systems

Autoren: Akhmetova, D. Kestor, G. Gioiosa, R. et al.

Quelle: Proceedings - IEEE International Conference on Cluster Computing, ICCC. :428-437

Schlagwörter: Scheduling overhead, Task granularity, Task-based programming models, Task-based schedulers, Cluster computing, Computer architecture, Directed graphs, Sensitivity analysis, Supercomputers, Application behaviors, Application performance, Directed acyclic graph (DAG), Processing elements, Programming models, Shared memory system, Task-based, Scheduling

Dateibeschreibung: print

Zugangs-URL: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-186853