Výsledky vyhledávání - "Spiking Neural Network Architecture"

ModNEF : An Open Source Modular Neuromorphic Emulator for FPGA for Low-Power In-Edge Artificial Intelligence

Autoři: Aurélie Saulquin Mazdak Fatahi Pierre Boulet a další

Přispěvatelé: Aurélie Saulquin Mazdak Fatahi Pierre Boulet a další

Zdroj: ACM Transactions on Architecture and Code Optimization. 22:1-24

Témata: [INFO.INFO-AI] Computer Science [cs]/Artificial Intelligence [cs.AI], [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], Neuromorphic accelerator, Artificial Intelligence, Spiking Neural Network, [INFO.INFO-NE] Computer Science [cs]/Neural and Evolutionary Computing [cs.NE], Spiking Neural Network FPGA Neuromorphic accelerator Edge Computing Artificial Intelligence Spiking Neural Network Architecture Parallel Architecture Embbeded Artificial Intelligence, Edge Computing, Embbeded Artificial Intelligence, Parallel Architecture, FPGA, Spiking Neural Network Architecture, [INFO.INFO-ES] Computer Science [cs]/Embedded Systems

Popis souboru: application/pdf

Přístupová URL adresa: https://hal.science/hal-05033844v1/document
https://hal.science/hal-05033844v1
https://doi.org/10.1145/3730581

ModNEF : An Open Source Modular Neuromorphic Emulator for FPGA for Low-Power In-Edge Artificial Intelligence

Autoři: Saulquin, Aurélie Fatahi, Mazdak Boulet, Pierre a další

Přispěvatelé: Saulquin, Aurélie Fatahi, Mazdak Boulet, Pierre a další

Témata: Spiking Neural Network FPGA Neuromorphic accelerator Edge Computing Artificial Intelligence Spiking Neural Network Architecture Parallel Architecture Embbeded Artificial Intelligence, Spiking Neural Network, FPGA, Neuromorphic accelerator, Edge Computing, Artificial Intelligence, Spiking Neural Network Architecture, Parallel Architecture, Embbeded Artificial Intelligence

Popis souboru: application/octet-stream

Relation: ACM Transactions on Architecture and Code Optimization; http://hdl.handle.net/20.500.12210/129295

Dostupnost: https://hdl.handle.net/20.500.12210/129295

Resilience Analysis of Distributed Wireless Spiking Neural Networks

Autoři: Tamás Borsos Massimo Condoluci Marios Daoutis a další

Témata: Spiking Neural Network Architecture, Distributed Wireless AI, Traffic Prioritization

Relation: https://zenodo.org/communities/hexa-x/; https://zenodo.org/communities/eu/; https://zenodo.org/records/5786692; oai:zenodo.org:5786692; https://doi.org/10.1234/snnpreprint

Dostupnost: https://doi.org/10.1234/snnpreprint
https://zenodo.org/records/5786692

SpinNNaker: The world's biggest NoC

Autoři: Furber, S.

Zdroj: Furber, S 2014, SpinNNaker: The world's biggest NoC. in Networks-on-Chip (NoCS), 2014 Eighth IEEE/ACM International Symposium on. pp. ii-ii. https://doi.org/10.1109/NOCS.2014.7008754

Témata: microprocessor chips, 02 engineering and technology, network routing, deadlock avoidance, 7. Clean energy, ARM processor cores, silicon area, Abstracts, spike information, 0202 electrical engineering, electronic engineering, information engineering, Computer architecture, network-on-chip, asynchronous packet-switched fabric, Real-time systems, multicast algorithms, Computers, Modeling, silicon, spiking neural network architecture, fault-tolerance, network-on-chip communications, Educational institutions, 13. Climate action, integrated circuit modelling, SpinNNaker project, fault tolerance, Si, integer cores, size 10 m, neural net architecture, Biological neural networks, NoC

Přístupová URL adresa: https://ieeexplore.ieee.org/document/7008754/
https://www.research.manchester.ac.uk/portal/en/publications/spinnnaker-the-worlds-biggest-noc(2df7e8ce-b86d-459e-8798-e3d5ca96d5e3).html
https://dblp.uni-trier.de/db/conf/nocs/nocs2014.html#Furber14

Neuromorphic electronic circuits for building autonomous cognitive systems

Autoři: Chicca, E. Stafanini, F. Bartolozzi, C. a další

Zdroj: Proceedings of the IEEE, 102 (9)

Témata: Cognitive systems, Learning systems, Neuromorphic engineering, Real-time neuromorphic engineering, Spike-timing-dependent plasticity (STDP), Spiking neural network architecture, Subthreshold analog circuits, Very large scale integration (VLSI), Winner-take-all (WTA)

Relation: info:eu-repo/semantics/altIdentifier/wos/000344481800007; http://hdl.handle.net/20.500.11850/89393

Dostupnost: https://hdl.handle.net/20.500.11850/89393