Výsledky vyhledávání - "Simulation and Modeling|Model Development General Terms Layer assignment"

Wiring layer assignments with consistent stage delay

Autoři: Andrew B. Kahng Dirk Stroobandty The Pennsylvania State University CiteSeerX Archives

Přispěvatelé: Andrew B. Kahng Dirk Stroobandty The Pennsylvania State University CiteSeerX Archives

Zdroj: http://vlsicad.ucsd.edu/Publications/Conferences/107/c107.pdf.

Témata: Categories and Subject Descriptors B.7.2 [Hardware, Integrated Circuits|Placement and routing, J.6 [Computer Applications, Computer-Aided Engineering|CAD, I.6.5 [Computing Methodologies, Simulation and Modeling|Model Development General Terms Layer assignment, routing, delay, via impact, wire length. This

Popis souboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.501.1977; http://vlsicad.ucsd.edu/Publications/Conferences/107/c107.pdf

Dostupnost: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.501.1977
http://vlsicad.ucsd.edu/Publications/Conferences/107/c107.pdf