Suchergebnisse - "Run-Time Reconfiguration"

Comparative Analysis of FPGA with Network on Chip Architecture with Routing Techniques

Autoren: Satish, E. G. S. B., Rajeshwari T. R., Vinay et al.

Quelle: International Journal of Intelligent Systems and Applications in Engineering; Vol. 12 No. 19s (2024); 471-478

Schlagwörter: Run-Time Reconfiguration (RTR), Field programmable gateway array FPGA, Network on Chip, Reprogrammable Computing RC, programmable active memories PAM

Dateibeschreibung: application/pdf

Zugangs-URL: https://www.ijisae.org/index.php/IJISAE/article/view/5087

A Retargetable Compilation Framework for Heterogeneous Reconfigurable Computing

Autoren: Ul-Abdin, Zain Svensson, Bertil

Quelle: ELLIIT ACM Transactions on Reconfigurable Technology and Systems. 9(4)

Schlagwörter: Reconfigurable Processor Arrays, Run-time reconfiguration, Compiler Frameworks, Occam-pi

Dateibeschreibung: print

Zugangs-URL: https://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-30021
https://doi.org/10.1145/2843946

Speeding-up model-based fault injection of deep-submicron CMOS fault models through dynamic and partially reconfigurable FPGAS

Autoren: Andrés Martínez, David De

Weitere Verfasser: University/Department: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors

Thesis Advisors: Gil Vicente, Pedro Joaquín, Ruiz García, Juan Carlos

Quelle: Riunet

Schlagwörter: Inyección de fallos, Field programmable gate arrays (fpgas), Validación de circuitos de muy alta escala de integración (vlsi), Reconfiguración en tiempo de ejecución, Validation of very-large-scale in, Run-time reconfiguration, Fault injection, ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES, 3304 06, 3304 08, 3304 00

Zugangs-URL: http://hdl.handle.net/10251/1943

Speeding-up model-based fault injection of deep-submicron CMOS fault models through dynamic and partially reconfigurable FPGAS

Weitere Verfasser: University/Department: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors

Thesis Advisors: Gil Vicente, Pedro Joaquín, Ruiz García, Juan Carlos

Quelle: Riunet

Schlagwörter: Inyección de fallos, Field programmable gate arrays (fpgas), Validación de circuitos de muy alta escala de integración (vlsi), Reconfiguración en tiempo de ejecución, Validation of very-large-scale in, Run-time reconfiguration, Fault injection, ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES, 330406 - Arquitectura de ordenadores, 330408 - Fiabilidad de los ordenadores, 3304 - Tecnología de los ordenadores

Zugangs-URL: http://hdl.handle.net/10251/1943

VR-ZYCAP: A Versatile Resourse-Level ICAP Controller for ZYNQ SOC

Autoren: Bushra Sultana Anees Ullah Arsalan Ali Malik et al.

Quelle: Electronics, Vol 10, Iss 899, p 899 (2021)

Schlagwörter: run-time reconfiguration, ICAP controllers, ZynQ SoCs, Electronics, TK7800-8360

Relation: https://www.mdpi.com/2079-9292/10/8/899; https://doaj.org/toc/2079-9292; https://doaj.org/article/c64db0d77fc54ffebcb3a44197aa2803

Verfügbarkeit: https://doi.org/10.3390/electronics10080899
https://doaj.org/article/c64db0d77fc54ffebcb3a44197aa2803

EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures

Autoren: Stroobandt, Dirk Varbanescu, Ana Lucia Ciobanu, Catalin Bogdan et al.

Weitere Verfasser: Stroobandt, Dirk Varbanescu, Ana Lucia Ciobanu, Catalin Bogdan et al.

Quelle: ReCoSoC 2016
2016 11TH INTERNATIONAL SYMPOSIUM ON RECONFIGURABLE COMMUNICATION-CENTRIC SYSTEMS-ON-CHIP (RECOSOC)
2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)

Schlagwörter: Technology and Engineering, EXTRA, 02 engineering and technology, reconfigurable platform, Computer Networks and Communications, Hardware and Architecture, 3301 Architecture, 7. Clean energy, 4009 Electronics, Sensors and Digital Hardware, HPC, 0202 electrical engineering, electronic engineering, information engineering, exascale, QUANTUM MONTE-CARLO, 33 Built Environment and Design, 3303 Design, Run-time reconfiguration, FPGA, 40 Engineering

Dateibeschreibung: application/pdf

Zugangs-URL: https://biblio.ugent.be/publication/8059925/file/8700864.pdf
http://hdl.handle.net/10044/1/43205
https://hdl.handle.net/11311/1003724
https://doi.org/10.1109/ReCoSoC.2016.7533896
http://doi.org/10.1109/ReCoSoC.2016.7533896
http://hdl.handle.net/1854/LU-8059925
https://biblio.ugent.be/publication/8059925
https://biblio.ugent.be/publication/8059925/file/8700864

An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs

Autoren: Anees Ullah Ernesto Sanchez Luis Andres Cardona et al.

Quelle: Microelectronics Reliability. 75:110-120

Schlagwörter: ASIC fault emulation, Fault injection, Run-time reconfiguration (RTR), Electronic, Optical and Magnetic Materials, Atomic and Molecular Physics, and Optics, Condensed Matter Physics, Safety, Risk, Reliability and Quality, Surfaces, Coatings and Films, Electrical and Electronic Engineering, 13. Climate action, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, 01 natural sciences

Dateibeschreibung: application/pdf

Zugangs-URL: https://dialnet.unirioja.es/servlet/articulo?codigo=6128283
https://dblp.uni-trier.de/db/journals/mr/mr75.html#UllahSSCF17
https://doi.org/10.1016/j.microrel.2017.06.032
https://www.sciencedirect.com/science/article/pii/S0026271417302202
https://hdl.handle.net/11583/2712990
https://doi.org/10.1016/j.microrel.2017.06.032
https://www.sciencedirect.com/science/article/pii/S0026271417302202

Run-time Reconfigurable Acceleration for Genetic Programming Fitness Evaluation in Trading Strategies

Autoren: Andreea-Ingrid Funie Paul Grigoras Pavel Burovskiy et al.

Weitere Verfasser: Andreea-Ingrid Funie Paul Grigoras Pavel Burovskiy et al.

Quelle: J Signal Process Syst
Journal of Signal Processing Systems

Schlagwörter: Technology, Science & Technology, Computer Science, Information Systems, Computer Hardware & Architecture, 05 social sciences, 0906 Electrical And Electronic Engineering, Engineering, Electrical & Electronic, Fitness evaluation, 02 engineering and technology, Genetic programming, Article, Engineering, Computer Science, 0502 economics and business, RULES, 0202 electrical engineering, electronic engineering, information engineering, Electrical & Electronic, Networking & Telecommunications, High-frequency trading, Run-time reconfiguration, Information Systems

Zugangs-URL: https://link.springer.com/content/pdf/10.1007%2Fs11265-017-1244-8.pdf
https://pubmed.ncbi.nlm.nih.gov/31998430
https://www.ncbi.nlm.nih.gov/pmc/articles/PMC6956885
https://dblp.uni-trier.de/db/journals/vlsisp/vlsisp90.html#FunieGBLS18
https://pubmed.ncbi.nlm.nih.gov/31998430/
https://link.springer.com/content/pdf/10.1007%2Fs11265-017-1244-8.pdf
https://paperity.org/p/79893990/run-time-reconfigurable-acceleration-for-genetic-programming-fitness-evaluation-in
https://spiral.imperial.ac.uk/bitstream/10044/1/52831/5/s11265-017-1244-8.pdf
http://hdl.handle.net/10044/1/52831

Design and implementation of reconfigurable DSP circuit architectures on FPGA

Autoren: Heron, Jean-Paul Stephen

Schlagwörter: 621.3192, Run time reconfiguration

Zugangs-URL: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.266712

Power measurements and analysis for dynamic circuit specialization

Autoren: Kulkarni, Amit Bonamy, Robin Stroobandt, Dirk

Quelle: 2015 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG)

Schlagwörter: Reconfiguration Power, Technology and Engineering, AXI-HWICAP, Clock gating, Dynamic Circuit Specialization, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, Power Measurements, 16. Peace & justice, Parameterized Design, Run-time reconfiguration, 7. Clean energy

Dateibeschreibung: application/pdf

Zugangs-URL: https://biblio.ugent.be/publication/6957840/file/7007666.pdf
https://biblio.ugent.be/publication/6957840/file/7007666.pdf
http://ieeexplore.ieee.org/document/7393336/
https://dblp.uni-trier.de/db/conf/reconfig/reconfig2015.html#KulkarniBS15
http://doi.org/10.1109/ReConFig.2015.7393336
https://doi.org/10.1109/ReConFig.2015.7393336
https://biblio.ugent.be/publication/6957840
http://hdl.handle.net/1854/LU-6957840
https://biblio.ugent.be/publication/6957840
https://biblio.ugent.be/publication/6957840/file/7007666

FASTER: Facilitating analysis and synthesis technologies for effective reconfiguration

Autoren: Pnevmatikatos, Dionisios N. Becker, T. Brokalakis, A. et al.

Quelle: Facilitating Analysis and Synthesis Technologies\nfor Effective Reconfiguration (FASTER) 15th Euromicro Conference on Digital System Design, DSD 2012; Cesme, Izmir; Turkey; 5 September 2012 through 8 September 2012. :234-241

Schlagwörter: reconfigurable computing, run-time reconfiguration, tools for reconfiguration, relocation, partial reconfiguration, run-time system

Dateibeschreibung: electronic

Zugangs-URL: https://research.chalmers.se/publication/174055
http://publications.lib.chalmers.se/records/fulltext/174055/local_174055.pdf

A novel tool flow for increased routing configuration similarity in multi-mode circuits

Autoren: Al Farisi B. Vansteenkiste E. Bruneel K. et al.

Quelle: Proceedings (IEEE Computer Society Annual Symposium on VLSI. Print)
Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

Schlagwörter: Computer-Aided Design (CAD), Technology and Engineering, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, Run-time reconfiguration, 01 natural sciences, FPGA

Dateibeschreibung: application/pdf

Zugangs-URL: https://biblio.ugent.be/publication/4325950/file/4358734.pdf
https://biblio.ugent.be/publication/4325950/file/4358734.pdf
https://biblio.ugent.be/publication/4325950
https://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2013.html#FarisiVBS13
https://biblio.ugent.be/publication/4325950
https://biblio.ugent.be/publication/4325950/file/4358734
http://hdl.handle.net/1854/LU-4325950

System-level modelling of dynamic reconfigurable designs using functional programming abstractions

Autoren: Jan Kuper Bahram N. Uchevler Kjetil Svarstad et al.

Quelle: International Symposium on Quality Electronic Design (ISQED). :379-385

Schlagwörter: IR-87636, 0209 industrial biotechnology, EWI-23903, 02 engineering and technology, Self-Reconfiguration, digital circuit verification, Functional HDL, dynamic reconfigurable designs, functional programming abstractions, 0202 electrical engineering, electronic engineering, information engineering, logic design, high-level descriptions, Suzaku-sz410 board, high-level Haskell descriptions, EC Grant Agreement nr.: FP7/248465, synthesizable VHDL, FPGA Design, Higher-order functions, system-level modelling, Run-Time Reconfiguration, CLaSH tool, Field programmable gate arrays, run-time reconfigurable systems, METIS-302553, high-level structures, Formal verification, Partial Evaluation, RT level, partial evaluation implementation technique, Hardware Description Languages

Zugangs-URL: https://research.utwente.nl/en/publications/e0599eaa-a668-4fff-8849-86ec259851c2
https://doi.org/10.1109/ISQED.2013.6523639
https://ieeexplore.ieee.org/document/6523639/
https://research.utwente.nl/en/publications/system-level-modelling-of-dynamic-reconfigurable-designs-using-fu
https://dblp.uni-trier.de/db/conf/isqed/isqed2013.html#UchevlerSKB13

An Automatic Tool Flow for the Combined Implementation of Multi-mode Circuits

Autoren: Al Farisi, Brahim Bruneel, Karel Cardoso, João M. P. et al.

Quelle: DESIGN, AUTOMATION & TEST IN EUROPE

Schlagwörter: Technology and Engineering, run-time reconfiguration, Dynamic Circuit Specialization, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, 01 natural sciences, FPGA

Dateibeschreibung: application/pdf

Zugangs-URL: https://biblio.ugent.be/publication/4134604/file/4134620.pdf
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6513620
https://dl.acm.org/doi/10.5555/2485288.2485487
https://dblp.uni-trier.de/db/conf/date/date2013.html#FarisiBCS13
https://biblio.ugent.be/publication/4134604/file/4134620.pdf
https://biblio.ugent.be/publication/4134604
https://ieeexplore.ieee.org/document/6513620/
http://hdl.handle.net/1854/LU-4134604
https://biblio.ugent.be/publication/4134604/file/4134620
https://biblio.ugent.be/publication/4134604

Maximizing the reuse of routing resources in a reconfiguration-aware connection router

Autoren: Vansteenkiste, Elias Bruneel, Karel Stroobandt, Dirk et al.

Weitere Verfasser: Vansteenkiste, Elias Bruneel, Karel Stroobandt, Dirk et al.

Quelle: 2012 22nd International Conference on Field Programmable Logic and Applications (FPL)

Schlagwörter: Field-Programmable Gate Array, Technology and Engineering, Pathfinder, Fine-Grain Run-time Reconfiguration, Parameterised Configurations, 0202 electrical engineering, electronic engineering, information engineering, Routing algorithm, 02 engineering and technology, FPGA

Dateibeschreibung: application/pdf

Zugangs-URL: https://biblio.ugent.be/publication/3220107/file/3220123.pdf
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6339225
https://dblp.uni-trier.de/db/conf/fpl/fpl2012.html#VansteenkisteBS12
http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000006339225
https://biblio.ugent.be/publication/3220107/file/3220123.pdf
http://ieeexplore.ieee.org/document/6339225/
https://biblio.ugent.be/publication/3220107
http://hdl.handle.net/1854/LU-3220107
http://doi.org/10.1109/FPL.2012.6339225
https://biblio.ugent.be/publication/3220107/file/3220123
https://biblio.ugent.be/publication/3220107

Memory-Efficient and Fast Run-Time Reconfiguration of Regularly Structured Designs

Autoren: Al Farisi B. Heyse K. Bruneel K. et al.

Quelle: Field Programmable Logic and Applications, 21st International conference, Proceedings
Proceedings-21st International Conference on Field Programmable Logic and Applications, FPL 2011

Schlagwörter: SRL, Technology and Engineering, Run-time Reconfiguration, ICAP, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, Tunable LUT circuit, FPGA

Dateibeschreibung: application/pdf

Zugangs-URL: https://biblio.ugent.be/publication/1864276/file/1864285.pdf
https://biblio.ugent.be/publication/1864276
https://biblio.ugent.be/publication/1864276/file/1864285
http://hdl.handle.net/1854/LU-1864276

Run-Time Reconfiguration for Automatic Hardware/Software Partitioning

Autoren: Davidson, Tom Bruneel, Karel Stroobandt, Dirk et al.

Weitere Verfasser: Davidson, Tom Bruneel, Karel Stroobandt, Dirk et al.

Quelle: Proceedings 2010 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2010)

Schlagwörter: Technology and Engineering, AES, run-time reconfiguration, dynamic reconfiguration, hardware/software partitioning, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, FPGA

Dateibeschreibung: application/pdf

Zugangs-URL: https://biblio.ugent.be/publication/1105031/file/1148368.pdf
https://dblp.uni-trier.de/db/conf/reconfig/reconfig2010.html#DavidsonBS10
https://biblio.ugent.be/publication/1105031
https://biblio.ugent.be/publication/1105031/file/1148368.pdf
https://www.computer.org/csdl/proceedings/reconfig/2010/4314/00/4314a424.pdf
http://ieeexplore.ieee.org/document/5695343/
http://doi.org/10.1109/ReConFig.2010.57
http://hdl.handle.net/1854/LU-1105031
https://biblio.ugent.be/publication/1105031/file/1148368
https://biblio.ugent.be/publication/1105031

A user-centric composition model for the Internet of Services

Autoren: CORRADI, ANTONIO LODOLO, ENRICO MONTI, STEFANO et al.

Quelle: 2008 IEEE Symposium on Computers and Communications. :110-117

Schlagwörter: Internet of Services, dynamic and ever-growing scenario, service composition platforms, run time reconfiguration, flexibility and extensibility, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology

Zugangs-URL: http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000004625715
https://dblp.uni-trier.de/db/conf/iscc/iscc2008.html#CorradiLMP08
https://ieeexplore.ieee.org/document/4625715/
https://hdl.handle.net/11585/119539
https://doi.org/10.1109/ISCC.2008.4625715

EMMA - A suggestion for an embedded multi-precision multiplier array for FPGAs

Autoren: Pfänder, Oliver A. Pfleiderer, Hans-Jörg

Quelle: 2008 International Conference on Field Programmable Logic and Applications. :435-438

Schlagwörter: Multi-precision, Field programmable gate array, Field programmable gate arrays, 02 engineering and technology, 01 natural sciences, Digitale Signalverarbeitung, Baugh-Wooley, 0103 physical sciences, EMMA, 0202 electrical engineering, electronic engineering, information engineering, DSP, Run-time reconfiguration, FPGA

Dateibeschreibung: application/pdf

Zugangs-URL: https://oparu.uni-ulm.de/xmlui/bitstream/123456789/1038/1/vts_6528_8884.pdf
http://dblp.uni-trier.de/db/conf/fpl/fpl2008.html#PfanderP08
https://oparu.uni-ulm.de/xmlui/bitstream/123456789/1038/1/vts_6528_8884.pdf
https://dblp.uni-trier.de/db/conf/fpl/fpl2008.html#PfanderP08
http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000004629977
https://oparu.uni-ulm.de/xmlui/handle/123456789/1038
https://ieeexplore.ieee.org/document/4629977/

A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms

Autoren: Juan Antonio Clemente Ivan Beretta RANA, VINCENZO et al.

Weitere Verfasser: Juan Antonio Clemente Ivan Beretta RANA, VINCENZO et al.

Quelle: Docta Complutense
instname
E-Prints Complutense. Archivo Institucional de la UCM
E-Prints Complutense: Archivo Institucional de la UCM
Universidad Complutense de Madrid

Schlagwörter: Reconfigurable systems, Task scheduling, Hardware, Mapping, Reconfiguration overheads, 13. Climate action, 0202 electrical engineering, electronic engineering, information engineering, 004.312, 02 engineering and technology, Run-time reconfiguration

Dateibeschreibung: application/pdf

Zugangs-URL: http://eprints.ucm.es/39516/1/A%20Mapping-Scheduling%20Algorithm%20for%20Hardware%20Acceleration%20on%20Reconfigurable%20Platforms.pdf
https://hdl.handle.net/20.500.14352/35260
https://dblp.uni-trier.de/db/journals/trets/trets7.html#ClementeBRAS14
https://dl.acm.org/doi/10.1145/2611562
https://eprints.ucm.es/id/eprint/39516/
https://re.public.polimi.it/handle/11311/863338
https://doi.org/10.1145/2611562
https://infoscience.epfl.ch/record/195801
https://hdl.handle.net/11311/863338
https://doi.org/10.1145/2611562