Výsledky vyhľadávania - "Modulo multiplication algorithm"

The specifics of the Galois field GF(257) and its use for digital signal processing

Autori: Akhat Bakirov Dinara Matrassulova Yelizaveta Vitulyova a ďalší

Zdroj: Scientific Reports, Vol 14, Iss 1, Pp 1-15 (2024)

Predmety: Galois fields, Mersenne numbers, Quasi-cyclic permutations, Digital logarithm, Modulo multiplication algorithm, UAV flight computers, Medicine, Science

Popis súboru: electronic resource

Relation: https://doaj.org/toc/2045-2322

Prístupová URL adresa: https://doaj.org/article/eb2eeff1a4d141dda552ece02ab0f2c6

Optimization and implementation of Montgomery algorithm based on SM2 encryption.

Autori: Cai, Mian Wang, Lei

Zdroj: Proceedings of SPIE; 9/2/2023, Vol. 12642, p126421Q-126421Q-7, 1p

VLSI implementation of public-key encryption algorithms.

Autori: Orton, G. A. Roy, M. P. Scott, P. A. a ďalší

Zdroj: Advances in Cryptology - CRYPTO 86; 1987, p277-301, 25p

GENERALIZED ALGORITHMS FOR BINARY MODULO MULTIPLICATION AND MULTIPLICATION-DIVISION.

Autori: AMIN, ALAAELDIN

Zdroj: Journal of Circuits, Systems & Computers; Dec2010, Vol. 19 Issue 8, p1797-1815, 19p

Predmety: ALGORITHMS, GENERALIZATION, BINARY number system, MULTIPLICATION, MATHEMATICAL mappings, COMPUTER arithmetic, CRYPTOGRAPHY, DIVISION

Efficient Implementation of Cryptographic Arithmetic Primitives Using Reversible Logic and Vedic Mathematics.

Autori: Kiran Kumar, V. G. Shantharama Rai, C.

Zdroj: Journal of the Institution of Engineers (India): Series B; Feb2021, Vol. 102 Issue 1, p59-74, 16p

Radix-3 low-complexity modulo-M multipliers

Autori: Ioannis Kouretas Vassilis Paliouras

Zdroj: 2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS). :107-112

Predmety: 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, 01 natural sciences

Prístupová URL adresa: https://dblp.uni-trier.de/db/conf/patmos/patmos2019.html#KouretasP19
https://ieeexplore.ieee.org/document/8862036/

A 6.3nJ/op low energy 160-bit modulo-multiplier for elliptic curve cryptography processor.

Autori: Hyejung Kim Yongsang Kim Hoi-Jun Yoo

Zdroj: 2008 IEEE International Symposium on Circuits & Systems; 2008, p3310-3313, 4p

Improved ZDN-arithmetic for fast modulo multiplication.

Autori: Ploog, H. Flugel, S. Timmermann, D.

Zdroj: Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers & Processors. ICCD 2001; 2001, p166-171, 6p

A 6.3nJ/op low energy 160-bit modulo-multiplier for elliptic curve cryptography processor

Autori: Yongsang Kim Hoi-Jun Yoo Hyejung Kim

Zdroj: 2008 IEEE International Symposium on Circuits and Systems (ISCAS). :3310-3313

Predmety: 0103 physical sciences, 0101 mathematics, 01 natural sciences, 3. Good health

Prístupová URL adresa: http://ssl.kaist.ac.kr/2007/data/conference/yongsangkim_ISCAS2008.pdf
https://koasas.kaist.ac.kr/handle/10203/6388
https://dblp.uni-trier.de/db/conf/iscas/iscas2008.html#KimKY08
http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000004542166
http://dblp.uni-trier.de/db/conf/iscas/iscas2008.html#KimKY08
https://koasas.kaist.ac.kr/bitstream/10203/6388/1/yongsangkim_ISCAS2008.pdf
https://ieeexplore.ieee.org/document/4542166

Improved ZDN-arithmetic for fast modulo multiplication

Autori: Dirk Timmermann S. Flugel Hagen Ploog

Zdroj: Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001. :166-171

Predmety: 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, 01 natural sciences, 0105 earth and related environmental sciences

Prístupová URL adresa: http://www.amd.e-technik.uni-rostock.de/veroeff/plo_01_iccd.pdf
https://dblp.uni-trier.de/db/conf/iccd/iccd2001.html#PloogFT01
https://www.amd.e-technik.uni-rostock.de/veroeff/plo_01_iccd.pdf

VLSI implementation of modulo multiplication using carry free addition.

Autori: Sarkar, P. Roy, B.K. Choudhury, P.P.

Zdroj: Proceedings Tenth International Conference on VLSI Design; 1997, p457-460, 4p

Memory Conflict Analysis and Implementation of a Re-configurable Interleaver Architecture Supporting Unified Parallel Turbo Decoding.

Autori: Rizwan Asghar Di Wu Eilert, Johan a ďalší

Zdroj: Journal of Signal Processing Systems for Signal, Image & Video Technology; Jul2010, Vol. 60 Issue 1, p15-29, 15p, 19 Diagrams, 6 Charts

Fast Algorithms for Implementation of Montgomery's Modular Multiplication Technique.

Autori: Mohan, P.V. Ananda

Zdroj: Circuits, Systems & Signal Processing; Dec2004, Vol. 23 Issue 6, p463-478, 16p

A systolic architecture for modulo multiplication

Autori: Elleithy, Khaled M. Bayoumi, Magdy A.

Prispievatelia: Elleithy, Khaled M. Bayoumi, Magdy A.

Zdroj: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 42:725-729

Predmety: 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology

Prístupová URL adresa: https://core.ac.uk/display/52955707
http://ieeexplore.ieee.org/document/475251/
https://scholarworks.bridgeport.edu/xmlui/handle/123456789/446
https://ieeexplore.ieee.org/document/475251/

Testing a High-Speed Data Path The Design of the RSAb Crypto Chip

Autori: Mayerwieser, Wolfgang Posch, Karl Posch, Reinhard a ďalší

Predmety: high speed multipliers, hardware algorithms, design for testability, public key cryptography

Relation: https://zenodo.org/records/6995168; oai:zenodo.org:6995168

Dostupnosť: https://doi.org/10.3217/jucs-001-11-0728
https://zenodo.org/records/6995168

Radix-8 Booth Encoded Modulo 2 ^n -1 Multipliers With Adaptive Delay for High Dynamic Range Residue Number System.

Autori: Muralidharan, Ramya Chang, Chip-Hong

Zdroj: IEEE Transactions on Circuits & Systems. Part I: Regular Papers; May2011, Vol. 58 Issue 5, p982-993, 12p

Predmety: MODULI theory, MULTIPLICATION, PUBLIC key cryptography, MULTIPLIERS (Mathematical analysis), BINARY number system, ENERGY consumption

Obtaining optimum minimum points of error functions: a neural network approach.

Autori: Olivier, J.C.

Zdroj: IEEE Transactions on Circuits & Systems Part II: Analog & Digital Signal Processing; 1995, Vol. 42 Issue 11, p722-725, 4p

A Low-Complexity High-Radix RNS Multiplier.

Autori: Kouretas, loannis Paliouras, Vassilis

Zdroj: IEEE Transactions on Circuits & Systems. Part I: Regular Papers; Nov2009, Vol. 56 Issue 11, p2449-2462, 14p, 9 Charts, 11 Graphs

Predmety: MODULAR arithmetic, COMPUTER arithmetic, MULTIPLIERS (Mathematical analysis), ELECTRONIC circuits, ALGORITHMS

A Universal Architecture for Designing Efficient Modulo 2ⁿ + 1 Multipliers.

Autori: Sousa, Leonel Chaves, Ricardo

Zdroj: IEEE Transactions on Circuits & Systems. Part I: Regular Papers; Jun2005, Vol. 52 Issue 6, p1166-1178, 13p

Predmety: COMPLEMENTARY metal oxide semiconductors, ANALOG multipliers, MECHANICAL efficiency, ELECTRONIC structure, DIGITAL electronics, LOGIC circuits

A Modulo Multiplication Hardware Design

Autori: Gutub, Adnan

Predmety: Math, Computer, Systems, Electrical

Popis súboru: application/pdf; text/html

Relation: https://eprints.kfupm.edu.sa/id/eprint/1291/1/Project_Rep_2000.pdf; https://eprints.kfupm.edu.sa/id/eprint/1291/2/Project_Rep_2000_Abstract.pdf; https://eprints.kfupm.edu.sa/id/eprint/1291/3/Project_Rep_2000_Abstract.htm; (2000) A Modulo Multiplication Hardware Design. Project Report. Professor C. Koc, Oregon State University, ECE 575 Project Report.; Winter 2000

Dostupnosť: https://eprints.kfupm.edu.sa/id/eprint/1291/
https://eprints.kfupm.edu.sa/id/eprint/1291/1/Project_Rep_2000.pdf
https://eprints.kfupm.edu.sa/id/eprint/1291/2/Project_Rep_2000_Abstract.pdf
https://eprints.kfupm.edu.sa/id/eprint/1291/3/Project_Rep_2000_Abstract.htm
http://islab.oregonstate.edu/koc/ece575/00Project/Gutub.pdf