Suchergebnisse - "Microprocessor architectures"

Microprocessor 1: Prolegomena – Calculation and Storage Functions – Models of Computation and Computer Architecture

Autoren: Darche, Philippe

Weitere Verfasser: Darche, Philippe

Schlagwörter: [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], Microprocessor architectures, 7. Clean energy

Zugangs-URL: https://hal.science/hal-03120694v1

Power estimation of system-level buses for microprocessor-based architectures: a case study

Autoren: FORNACIARI, WILLIAM SCIUTO, DONATELLA SILVANO, CRISTINA

Quelle: Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040). :131-136

Schlagwörter: Microprocessor Architectures, Power Estimation, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology

Dateibeschreibung: application/pdf

Zugangs-URL: https://dblp.uni-trier.de/db/conf/iccd/iccd1999.html#FornaciariSS99
https://ieeexplore.ieee.org/document/808417/
http://doi.ieeecomputersociety.org/10.1109/ICCD.1999.808417
https://hdl.handle.net/11311/692378
https://doi.org/10.1109/ICCD.1999.808417

Architecture and design methodology of a 32-bit microprocessor

Autoren: F. Bozzetti SILVANO, CRISTINA

Quelle: [1991] Proceedings, Advanced Computer Technology, Reliable Systems and Applications. :613-617

Schlagwörter: Microprocessor Architectures

Dateibeschreibung: application/pdf

Zugangs-URL: https://ieeexplore.ieee.org/document/257460/
http://ieeexplore.ieee.org/document/257460/
https://hdl.handle.net/11311/692419
https://doi.org/10.1109/CMPEUR.1991.257460

Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach

Autoren: M. Monchiero PALERMO, GIANLUCA SAMI, MARIAGIOVANNA et al.

Quelle: Integration. 38:515-524

Schlagwörter: 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, Microprocessor Architectures, VLIW Processors, Branch prediction, Low-power Design, 7. Clean energy

Dateibeschreibung: application/pdf

Low-power data forwarding for VLIW embedded architectures

Autoren: SAMI, MARIAGIOVANNA SCIUTO, DONATELLA SILVANO, CRISTINA et al.

Quelle: IEEE transactions on very large scale integration (VLSI) systems
info:cnr-pdr/source/autori:Sami M., Sciuto D., Silvano C., Zaccaria V., Zafalon R./titolo:Low-Power Data Forwarding for VLIW Embedded Architectures/doi:/rivista:IEEE transactions on very large scale integration (VLSI) systems (Print)/anno:2002/pagina_da:/pagina_a:/intervallo_pagine:/volume:10

Schlagwörter: Microprocessor Architectures, VLIW Processors, Pipelined Processors, Compilers, Low-power design, Embedded Systems

Dateibeschreibung: application/pdf

Zugangs-URL: http://www.cnr.it/prodotto/i/20383
https://publications.cnr.it/doc/20383
https://dblp.uni-trier.de/db/journals/tvlsi/tvlsi10.html#SamiSSZZ02
https://ieeexplore.ieee.org/document/1178085/
http://home.deib.polimi.it/zaccaria/2.0/pdf/J2.pdf
https://www.infona.pl/resource/bwmeta1.element.ieee-art-000001178085
http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000001178085
https://re.public.polimi.it/handle/11311/256819
http://doi.ieeecomputersociety.org/10.1109/TVLSI.2002.801617
https://hdl.handle.net/11311/256819
https://doi.org/10.1109/TVLSI.2002.801617

The impact of instruction set orthogonality on compiler code generation

Autoren: Williams, Fleur Liane

Schlagwörter: 005, Microprocessor architectures

Zugangs-URL: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.252688

Transforming TLP into DLP with the dynamic inter-thread vectorization architecture

Transformer le TLP en DLP avec l'architecture de vectorisation dynamique inter-thread

Autoren: Kalathingal, Sajith

Thesis Advisors: Rennes 1, Seznec, André, Collange, Sylvain

Schlagwörter: Multi-Threading simultané, SPMD, SIMD, Vectorisation dynamique, Architectures des microprocesseurs, Simultaneous Multi-Threading, Dynamic inter-Thread vectorization, Microprocessor architectures

Verfügbarkeit: http://www.theses.fr/2016REN1S133/document

Transforming TLP into DLP with the dynamic inter-thread vectorization architecture ; Transformer le TLP en DLP avec l'architecture de vectorisation dynamique inter-thread

Autoren: Kalathingal, Sajith Inria Rennes – Bretagne Atlantique Institut National de Recherche en Informatique et en Automatique (Inria) et al.

Weitere Verfasser: Kalathingal, Sajith Inria Rennes – Bretagne Atlantique Institut National de Recherche en Informatique et en Automatique (Inria) et al.

Quelle: https://theses.hal.science/tel-01426915 ; Hardware Architecture [cs.AR]. Université de Rennes, 2016. English. ⟨NNT : 2016REN1S133⟩.

Schlagwörter: Simultaneous Multi-Threading, SPMD, SIMD, Dynamic inter-Thread vectorization, Microprocessor architectures, Multi-Threading simultané, Vectorisation dynamique, Architectures des microprocesseurs, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: NNT: 2016REN1S133

Verfügbarkeit: https://theses.hal.science/tel-01426915
https://theses.hal.science/tel-01426915v3/document
https://theses.hal.science/tel-01426915v3/file/KALATHINGAL_Sajith.pdf

Experimental characterization of CMOS photonic devices

Autoren: Gómez Gonzalvo, Alberto Universitat Politècnica de Catalunya. Departament de Teoria del Senyal i Comunicacions Massachusetts Institute of Technology et al.

Weitere Verfasser: Gómez Gonzalvo, Alberto Universitat Politècnica de Catalunya. Departament de Teoria del Senyal i Comunicacions Massachusetts Institute of Technology et al.

Schlagwörter: Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Telecomunicació òptica::Fotònica, Optical communications, Photonics, PN junctions, Fibra óptica, Circuits MOS, Fotònica, Fibres òptiques, Silicon photonics, Optical fiber, Experimental results, Optical networks, Microprocessor architectures, Uniones PN, Resultados experimentales, Redes ópticas, Arquitectura de microprocesadores, Comunicacions òptiques

Dateibeschreibung: application/pdf

Relation: http://infoteleco.upc.edu/incoming/pfc/130046/poster_final_5_HDiMbN.pdf; http://hdl.handle.net/2117/91823

Verfügbarkeit: http://hdl.handle.net/2117/91823

Processor architecture with variable-stage pipeline

Autoren: SAMI, MARIAGIOVANNA SCIUTO, DONATELLA SILVANO, CRISTINA et al.

Schlagwörter: Microprocessor Architectures, Low-Power Design

Dateibeschreibung: application/pdf

Zugangs-URL: https://hdl.handle.net/11311/569401

An investigation on the applicability of multi-microprocessing in the two dimensional digital filtering problem

Autoren: Whitcher, Timothy J.

Quelle: Theses

Schlagwörter: Digital image processing, Fast fourier transform, Microprocessors, Microprocessor architectures, Z8000 microprocessor

Dateibeschreibung: application/pdf

Relation: https://repository.rit.edu/theses/5647; https://repository.rit.edu/context/theses/article/6651/viewcontent/TWhitcherThesis05_1980.pdf

Verfügbarkeit: https://repository.rit.edu/theses/5647
https://repository.rit.edu/context/theses/article/6651/viewcontent/TWhitcherThesis05_1980.pdf

Experimental characterization of CMOS photonic devices

Autoren: Universitat Politècnica de Catalunya. Departament de Teoria del Senyal i Comunicacions Massachusetts Institute of Technology Ram, Rajeev J. et al.

Index Begriffe: Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Telecomunicació òptica::Fotònica, Optical communications, Photonics, PN junctions, Fibra óptica, Circuits MOS, Fotònica, Fibres òptiques, Silicon photonics, Optical fiber, Experimental results, Optical networks, Microprocessor architectures, Uniones PN, Resultados experimentales, Redes ópticas, Arquitectura de microprocesadores, Comunicacions òptiques, Master thesis

URL: https://hdl.handle.net/2117/91823
http://infoteleco.upc.edu/incoming/pfc/130046/poster_final_5_HDiMbN.pdf
http://infoteleco.upc.edu/incoming/pfc/130046/poster_final_5_HDiMbN.pdf