Výsledky vyhľadávania - "Low-Power VLSI Circuit Design and Optimization"

Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis

Autori: Youwei Xiao Zizhang Luo Kexing Zhou a ďalší

Zdroj: Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays. :211-222

Predmety: Parallel computing, Cement, Computer hardware, Low-Power VLSI Circuit Design and Optimization, Reconfigurable Computing Systems and Design Methods, Computer science, Materials science, Field-programmable gate array, Systems engineering, 12. Responsible consumption, Engineering, Hardware and Architecture, Design cycle, Computer Science, Physical Sciences, Metallurgy, FOS: Electrical engineering, electronic engineering, information engineering, Parallel Computing and Performance Optimization, Computer architecture, Electrical and Electronic Engineering, Embedded system

Hybrid Data Driven Clock Gating and Data Gating Technique for Better Saving Power in ALU RISC-V

Autori: Minh Vo

Zdroj: International Journal of Electrical and Electronics Research. 12:238-246

Predmety: Instruction set, Clock skew, Jitter, 02 engineering and technology, Quantum mechanics, 7. Clean energy, Engineering, Clock gating, Clock signal, 0202 electrical engineering, electronic engineering, information engineering, FOS: Electrical engineering, electronic engineering, information engineering, Psychology, Electrical and Electronic Engineering, Reduced instruction set computing, Physics, Transistor, Computer hardware, Voltage, Low-Power VLSI Circuit Design and Optimization, Power (physics), Reconfigurable Computing Systems and Design Methods, Power gating, Computer science, FOS: Psychology, Hardware and Architecture, Electrical engineering, Physical Sciences, Computer Science, Telecommunications, Very Large Scale Integration Testing, Gating, Neuroscience

Novel Lossless Positive-/Negative-Grounded Capacitance Multipliers Using VCII

Autori: Mohammad Faseehuddin Sadia Shireen Sawal Hamid Md Ali a ďalší

Zdroj: Elektronika ir Elektrotechnika, Vol 29, Iss 4, Pp 19-26 (2023)

Predmety: VLSI Circuits, grounded capacitance multiplier (gcm), multiplication factor, Electrode, Biomedical Engineering, Voltage source, Capacitance, Nanoelectronics and Transistors, FOS: Medical engineering, Quantum mechanics, 7. Clean energy, lossless capacitance multiplier, Engineering, FOS: Electrical engineering, electronic engineering, information engineering, Resistor, Current-Mode Circuits, second-generation voltage conveyor (vcii), Electrical and Electronic Engineering, Electronic engineering, Analog Circuit Design for Biomedical Applications, Physics, Double-Gate Transistors, Voltage, Capacitor, Low-Power VLSI Circuit Design and Optimization, Lossless compression, Computer science, TK1-9971, Negative impedance converter, Algorithm, Electrical engineering, Data compression, Physical Sciences, Electrical engineering. Electronics. Nuclear engineering

Prístupová URL adresa: https://doaj.org/article/189d44a74aa64618b52ab9b0d1e51184

A Unified Power-Delay Model for GDI Library Cell Created Using New Mux Based Signal Connectivity Algorithm

Autori: Jebashini Ponnian Senthil Pari Uma Ramadass a ďalší

Zdroj: Emerging Science Journal, Vol 7, Iss 4, Pp 1364-1394 (2023)

Predmety: Structural engineering, Electronic circuit, Nanoelectronics and Transistors, Node (physics), 02 engineering and technology, Quantum mechanics, 01 natural sciences, 7. Clean energy, Multiplexing, Engineering, logical effort, FOS: Electrical engineering, electronic engineering, information engineering, 0202 electrical engineering, electronic engineering, information engineering, mux-based connectivity, T1-995, Electrical and Electronic Engineering, Technology (General), H1-99, Electronic engineering, Physics, CMOS, Transistor, Voltage, Multiplexer, Low-Power VLSI Circuit Design and Optimization, Power (physics), Computer science, gate diffusion technique, 0104 chemical sciences, Social sciences (General), Algorithm, Power Optimization, QA71-90 Instruments and machines, Electrical engineering, Physical Sciences, Design and Optimization of Field-Programmable Gate Arrays and Application-Specific Integrated Circuits, gdi library, Dynamic Load Balancing, power model

Popis súboru: text

Prístupová URL adresa: https://doaj.org/article/e0b2a8774ac04fc79b0623e27e11df56

Effects of logic glitch and (area-power dissipation) leakage on cryptosystems using clock gating technique to enhance web etiquette

Autori: Akhigbe-mudu Thursday Ehis

Zdroj: Brazilian Journal of Science. 2:38-52

Predmety: Energy Efficiency, Memristive Devices for Neuromorphic Computing, Subthreshold conduction, 02 engineering and technology, 01 natural sciences, 7. Clean energy, Engineering, Power Management, 11. Sustainability, 0202 electrical engineering, electronic engineering, information engineering, FOS: Electrical engineering, electronic engineering, information engineering, Parallel Computing and Performance Optimization, 0101 mathematics, Electrical and Electronic Engineering, Embedded system, Electronic engineering, CMOS, Transistor, Voltage, Low-Power VLSI Circuit Design and Optimization, Computer science, Leakage Reduction, Programming language, Energy consumption, Low-Power, Hardware and Architecture, Electrical engineering, Physical Sciences, Computer Science, Software portability, Glitch

A 1.0 fJ energy/bit single‐ended 1 kb 6T SRAM implemented using 40 nm CMOS process

Autori: Chua‐Chin Wang Ralph Gerard B. Sangalang I‐Ting Tseng a ďalší

Zdroj: IET Circuits, Devices & Systems. 17:75-87

Predmety: Silicon, Geometry, Electronic circuit, Nanoelectronics and Transistors, Strained-Silicon Technology, Static random-access memory, Die (integrated circuit), 02 engineering and technology, Quantum mechanics, 7. Clean energy, 01 natural sciences, Low voltage, Engineering, 0103 physical sciences, FOS: Electrical engineering, electronic engineering, information engineering, FOS: Mathematics, 0202 electrical engineering, electronic engineering, information engineering, Electrical and Electronic Engineering, Optoelectronics, Embedded system, Standby power, Electronic engineering, Physics, CMOS Scaling, CMOS, Voltage, Computer hardware, Low-Power VLSI Circuit Design and Optimization, Power (physics), Computer science, Materials science, Process (computing), Operating system, Atomic Layer Deposition Technology, Electrical engineering, Physical Sciences, Reduction (mathematics), Energy (signal processing), Mathematics

A Novel Multicriteria Optimization Technique for VLSI Floorplanning Based on Hybridized Firefly and Ant Colony Systems

Autori: B. Srinivasan Ramarathnam Venkatesan Belqasem Aljafari a ďalší

Zdroj: IEEE Access, Vol 11, Pp 14677-14692 (2023)

Predmety: Parallel computing, VLSI Circuits, ant colony optimization, Three-Dimensional Integrated Circuits, Chip, Metaheuristic, Firefly algorithm, 02 engineering and technology, Floorplan, Very-large-scale integration, 7. Clean energy, Engineering, VLSI floorplanning, Netlist, FOS: Electrical engineering, electronic engineering, information engineering, 0202 electrical engineering, electronic engineering, information engineering, Electrical and Electronic Engineering, Ant colony optimization algorithms, Embedded system, hybrid optimization method, Routing (electronic design automation), Geography, Electronic engineering, Particle swarm optimization, firefly optimization, Low-Power VLSI Circuit Design and Optimization, Computer science, TK1-9971, Algorithm, multi-objective optimization, Chip Stacking, Physical Sciences, Physical design, Telecommunications, Electrical engineering. Electronics. Nuclear engineering, Design and Optimization of Field-Programmable Gate Arrays and Application-Specific Integrated Circuits, Circuit design, Benchmark (surveying), Geodesy

Prístupová URL adresa: https://doaj.org/article/4b03ae60f8174308bb1c9db85cbd32ce

Optimization of Quantum Cost for Low Energy Reversible Signed/Unsigned Multiplier Using Urdhva-Tiryakbhyam Sutra

Autori: Marwa A. Elmenyawi Radwa M. Tawfeek

Zdroj: Computer Systems Science and Engineering. 46:1827-1844

Predmety: Economics, Macroeconomics, Electronic circuit, Multiplication algorithm, 02 engineering and technology, Latency (audio), Quantum mechanics, 7. Clean energy, Quantum, Multiplexing, Engineering, Artificial Intelligence, Quantum Computing and Simulation, Quantum computer, FOS: Electrical engineering, electronic engineering, information engineering, FOS: Mathematics, 0202 electrical engineering, electronic engineering, information engineering, Electrical and Electronic Engineering, Arithmetic, Physics, Multiplexer, Low-Power VLSI Circuit Design and Optimization, Computer science, Algorithm, Computational Theory and Mathematics, Reversible Logic, Adder, Electrical engineering, Computer Science, Physical Sciences, Telecommunications, Design and Simulation of Quantum-dot Cellular Automata, Multiplier (economics), Binary number, Mathematics

Design Techniques for Energy-Efficient Analog-to-Digital Converters

Autori: MoonHyung Jang Xiyuan Tang Yong Lim a ďalší

Zdroj: IEEE Open Journal of the Solid-State Circuits Society, Vol 3, Pp 145-161 (2023)

Predmety: continuous-time (CT), Phase-Locked Loops in High-Speed Circuits, Energy Efficiency, Biomedical Engineering, Electric apparatus and materials. Electric circuits. Electric networks, FOS: Medical engineering, 7. Clean energy, Bandwidth (computing), Engineering, Successive approximation ADC, FOS: Electrical engineering, electronic engineering, information engineering, FOS: Mathematics, Efficient energy use, energy efficient, Electrical and Electronic Engineering, TK452-454.4, noise-shaping (NS), low power, Electronic engineering, Analog Circuit Design for Biomedical Applications, Statistics, delta-sigma modulation, Voltage, Capacitor, Low-Power VLSI Circuit Design and Optimization, Converters, Computer science, Analog-to-digital converter (ADC), Electrical engineering, Physical Sciences, Telecommunications, Figure of merit, Computer vision, Energy (signal processing), Mathematics

Prístupová URL adresa: https://doaj.org/article/9be28b97db52404e958583909920f27f

Energy-Performance Optimization via P/N Ratio Sizing With Full Diffusion Layout Structure and Standard Cell Height Tuning in Near-Threshold Voltage Operation

Autori: Yang Wei Lim Noor Ain Kamsani Roslina Mohd Sidek a ďalší

Zdroj: IEEE Access, Vol 11, Pp 12536-12546 (2023)

Predmety: Integrated circuit, Energy Efficiency, Standard cell, Nanoelectronics and Transistors, 02 engineering and technology, 7. Clean energy, Visual arts, Engineering, FOS: Electrical engineering, electronic engineering, information engineering, FOS: Mathematics, 0202 electrical engineering, electronic engineering, information engineering, Efficient energy use, Electrical and Electronic Engineering, Sizing, energy efficiency, standard cell height, P/N ratio optimization, Electronic engineering, CMOS Scaling, High-Performance Nanoscale Devices, CMOS, Transistor, Statistics, near-threshold voltage, Voltage, Low-Power VLSI Circuit Design and Optimization, Computer science, TK1-9971, Energy consumption, Atomic Layer Deposition Technology, Electrical engineering, Physical Sciences, Electrical engineering. Electronics. Nuclear engineering, Energy (signal processing), CMOS digital integrated circuit, NMOS logic, Mathematics, Art

Prístupová URL adresa: https://doaj.org/article/42c45d80e3174ebfa249ea242fa2780b

Design of a Low Power CMOS Inverter with the VBB Stack Approach

Autori: S. Khmailia J. Rouabeh A. Mami

Zdroj: Engineering, Technology & Applied Science Research. 12:8891-8895

Predmety: Stack (abstract data type), Biomedical Engineering, Nanoelectronics and Transistors, 02 engineering and technology, FOS: Medical engineering, Quantum mechanics, 7. Clean energy, Engineering, FOS: Electrical engineering, electronic engineering, information engineering, 0202 electrical engineering, electronic engineering, information engineering, Inverter, Electrical and Electronic Engineering, Electronic engineering, Analog Circuit Design for Biomedical Applications, Physics, CMOS Scaling, CMOS, Voltage, Low-Power VLSI Circuit Design and Optimization, Power (physics), Computer science, Leakage Reduction, Programming language, Low-Power, Spice, Power consumption, Electrical engineering, Physical Sciences

Low Voltage High Performance CMOS Current Mode Four-Quadrant Analog Multiplier Circuit

Autori: Ettaghzouti, Thouraya Khlaifia, Dalila Zitouni, Naoufel a ďalší

Zdroj: Radioengineering, Vol 31, Iss 2, Pp 216-223 (2022)

Predmety: VLSI Circuits, Voltage multiplier, Economics, Biomedical Engineering, Macroeconomics, Nanoelectronics and Transistors, 02 engineering and technology, Quadrant (abdomen), FOS: Medical engineering, 7. Clean energy, four-quadrant, Analog multiplier, Engineering, current mode, cmos, FOS: Electrical engineering, electronic engineering, information engineering, Pathology, 0202 electrical engineering, electronic engineering, information engineering, Current-Mode Circuits, Low-Noise Amplifiers, low voltage, Electrical and Electronic Engineering, Multiplier, Dropout voltage, Electronic engineering, Analog Circuit Design for Biomedical Applications, CMOS Scaling, High-Performance Nanoscale Devices, CMOS, multiplier, Voltage, Low-Power VLSI Circuit Design and Optimization, Digital signal processing, Materials science, TK1-9971, Analog signal, Voltage reference, Electrical engineering, Physical Sciences, Medicine, Electrical engineering. Electronics. Nuclear engineering, translinear loop, Multiplier (economics)

Popis súboru: text; application/pdf

Prístupová URL adresa: https://doaj.org/article/1513c1036ec647c78285145e8776e3a6
http://hdl.handle.net/11012/204278

Experimental Findings on the Sources of Detected Unrecoverable Errors in GPUs

Autori: Fernando Fernandes dos Santos Sujit Malde Carlo Cazzaniga a ďalší

Zdroj: IEEE Transactions on Nuclear Science

Predmety: FOS: Computer and information sciences, Parallel computing, Interface (matter), Multiplication (music), Fault Tolerance, Compiler, Set (abstract data type), 01 natural sciences, Engineering, Error Detection, 0103 physical sciences, FOS: Electrical engineering, electronic engineering, information engineering, Parallel Computing and Performance Optimization, GPU Computing, Electrical and Electronic Engineering, Source code, Code (set theory), Bubble, Physics, Detected unrecoverable error (DUE), graphic processing units, radiation experiments, reliability, Acoustics, Low-Power VLSI Circuit Design and Optimization, Computer science, Programming language, Operating system, Fault Tolerance in Electronic Systems, Graphics processing unit, Computer Science - Distributed, Parallel, and Cluster Computing, Hardware and Architecture, Physical Sciences, Computer Science, Graphics, Distributed, Parallel, and Cluster Computing (cs.DC), Soft Errors, Transient Faults, Maximum bubble pressure method

Popis súboru: application/pdf

Prístupová URL adresa: http://arxiv.org/pdf/2108.00554
http://arxiv.org/abs/2108.00554
https://hdl.handle.net/11572/346651
https://doi.org/10.1109/TNS.2022.3141341
https://ieeexplore.ieee.org/document/9674902

Random Telegraph Noise Modeling for Circuit Analysis: RTN in Ring Oscillators

Autori: Mauricio Banaszeski da Silva Thiago H. Both Gilson I. Wirth

Zdroj: IEEE Journal of the Electron Devices Society, Vol 10, Pp 459-465 (2022)

Predmety: Artificial intelligence, jitter, Phase Noise, Organic chemistry, Jitter, Nanoelectronics and Transistors, Noise (video), 01 natural sciences, Engineering, Statistical Timing Analysis, ring oscillator (ROSC), 0103 physical sciences, FOS: Electrical engineering, electronic engineering, information engineering, FOS: Mathematics, Image (mathematics), Oscillators, Electrical and Electronic Engineering, Topology (electrical circuits), reliability, Radio Frequency Integrated Circuit Design, Electronic engineering, Ring (chemistry), 1/http://www.niso.org/schemas/ali/1.0/' xmlns:mml='http://www.w3.org/1998/Math/MathML' xmlns:xlink='http://www.w3.org/1999/xlink' xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'>f noise, Low-Power VLSI Circuit Design and Optimization, Computer science, TK1-9971, Chemistry, Random telegraph noise (RTN), Combinatorics, logic gates, Physical Sciences, Electrical engineering. Electronics. Nuclear engineering, Mathematics

Prístupová URL adresa: https://ieeexplore.ieee.org/ielx7/6245494/6423298/09695958.pdf
https://doaj.org/article/9a5f98abc5b74578b554557d070039d5

A New Perspective of Flexible Clocking Ideology for Driving and Devising Circuits in Emerging Resource-Constrained Applications

Autori: Xiangye Wei Liming Xiu

Zdroj: IEEE Access, Vol 10, Pp 25767-25785 (2022)

Predmety: IoT, Artificial intelligence, frequency synthesis, Memristive Devices for Neuromorphic Computing, FOS: Political science, Resource (disambiguation), Perspective (graphical), Chip, Jitter, FOS: Law, 02 engineering and technology, 7. Clean energy, Engineering, Hardware Security and Authentication Techniques, Statistical Timing Analysis, edge computing, Signal edge, Clock, Computer engineering, Clock signal, Clock rate, timing, FOS: Electrical engineering, electronic engineering, information engineering, 0202 electrical engineering, electronic engineering, information engineering, Computer architecture, Electrical and Electronic Engineering, Political science, Computer network, Electronic engineering, Obstacle, Computer hardware, Low-Power VLSI Circuit Design and Optimization, Digital signal processing, Computer science, Distributed computing, TK1-9971, Process (computing), Operating system, TAF-DPS, Analog signal, Hardware and Architecture, Physical Sciences, Computer Science, Telecommunications, Electrical engineering. Electronics. Nuclear engineering, Law

Prístupová URL adresa: https://ieeexplore.ieee.org/ielx7/6287639/6514899/09726207.pdf
https://doaj.org/article/3582e5e893714f0fb7c2253f3fe3a96a

Implementation of Booth Multiplier Algorithm using Radix-4 in FPGA

Autori: Abdul Halim Mokhtar Chew Sue Ping Muhamad Faiz Md Din a ďalší

Zdroj: Jurnal Kejuruteraan. :161-165

Predmety: Parallel computing, Economics, Macroeconomics, Latency (audio), Engineering, Artificial Intelligence, Quantum Computing and Simulation, FOS: Electrical engineering, electronic engineering, information engineering, FOS: Mathematics, Electrical and Electronic Engineering, Floating-Point Arithmetic in Scientific Computation, Arithmetic, Computer hardware, Low-Power VLSI Circuit Design and Optimization, FPGA Acceleration, Digital signal processing, Computer science, Verilog, Field-programmable gate array, Algorithm, Computational Theory and Mathematics, Adder, Physical Sciences, Computer Science, Telecommunications, Multiplier (economics), Booth's multiplication algorithm, Binary number, Mathematics

Analysis of Existing and Proposed 3-Bit and Multi-Bit Multiplier Algorithms for FIR Filters and Adaptive Channel Equalizers on FPGA

Autori: Aneela Pathan Tayab Din Memon Fareesa K. Sohu a ďalší

Zdroj: Quaid-e-Awam University Research Journal of Engineering Science & Technology. 19:81-89

Predmety: Parallel computing, Economics, Multiplication (music), Macroeconomics, Multiplierless Algorithms, FIR Filters, Latency (audio), 7. Clean energy, Engineering, FOS: Electrical engineering, electronic engineering, information engineering, FOS: Mathematics, Electrical and Electronic Engineering, Floating-Point Arithmetic in Scientific Computation, Advanced Techniques in Digital Signal Processing, Accuracy-Guaranteed Bit-Width Optimization, Arithmetic, Computer hardware, Finite impulse response, Low-Power VLSI Circuit Design and Optimization, Lookup table, FPGA Acceleration, Digital signal processing, Hardware Implementations, Computer science, 16-bit, Field-programmable gate array, Programming language, Algorithm, Computational Theory and Mathematics, Adder, Combinatorics, Computer Science, Physical Sciences, Signal Processing, Telecommunications, Multiplier (economics), Booth's multiplication algorithm, Mathematics

Prístupová URL adresa: http://publications.quest.edu.pk/ojs-3.1.1-4/index.php/qrj/article/download/278/106
http://publications.quest.edu.pk/ojs-3.1.1-4/index.php/qrj/article/download/278/106
http://publications.quest.edu.pk/ojs-3.1.1-4/index.php/qrj/article/view/278

Synthesis of Reversible and Quantum Circuit Using ROCBDD and Mixed-Polarity Toffoli Gate

Autori: Hieu Nguyen Linh H. Tran

Zdroj: IEEE Access, Vol 9, Pp 135432-135439 (2021)

Predmety: VLSI Circuits, Quantum circuit, synthesis, Memristive Devices for Neuromorphic Computing, Electronic circuit, 02 engineering and technology, Quantum error correction, Quantum mechanics, Resistive Switching, Quantum, Binary decision diagram, Engineering, Toffoli gate, Theoretical computer science, Artificial Intelligence, Quantum Computing and Simulation, Quantum computer, Boolean function, FOS: Electrical engineering, electronic engineering, information engineering, Genetics, 0202 electrical engineering, electronic engineering, information engineering, ROCBDD, Electrical and Electronic Engineering, Biology, reversible circuit, Fault-tolerant Quantum Computation, Quantum gate, Physics, Reversible computing, Logic gate, Low-Power VLSI Circuit Design and Optimization, Computer science, Mixed-polarity Toffoli gate, TK1-9971, Logic synthesis, Algorithm, FOS: Biological sciences, Computer Science, Physical Sciences, Polarity (international relations), Electrical engineering. Electronics. Nuclear engineering, Cell

Prístupová URL adresa: https://ieeexplore.ieee.org/ielx7/6287639/6514899/09552914.pdf
https://doaj.org/article/90498ceacd174fadaaa06cccbc7c982c
https://ieeexplore.ieee.org/document/9552914/references
https://dblp.uni-trier.de/db/journals/access/access9.html#Nguyen-TrungT21

Practical Full Chip Clock Distribution Design With a Flexible Topology and Hybrid Metaheuristic Technique

Autori: Eng Keong Teh Mohamad Adzhar Md Zawawi Mohamed Fauzi Packeer Mohamed a ďalší

Zdroj: IEEE Access, Vol 9, Pp 14816-14835 (2021)

Predmety: Artificial intelligence, Chip, Clock skew, Heuristic, Jitter, Skew, 02 engineering and technology, Engineering, Statistical Timing Analysis, Clock signal, FOS: Electrical engineering, electronic engineering, information engineering, 0202 electrical engineering, electronic engineering, information engineering, CMOS Design, clock distribution, Electrical and Electronic Engineering, Embedded system, System-on-a-chip (SoC), Topology (electrical circuits), hybrid meta-heuristic, Network topology, System on a chip, Low-Power VLSI Circuit Design and Optimization, artificial intelligence, Reconfigurable Computing Systems and Design Methods, Computer science, TK1-9971, Application-specific integrated circuit, Power Optimization, Operating system, Hardware and Architecture, Integrated circuit design, Electrical engineering, Physical Sciences, Computer Science, Reconfigurable Computing, Multiprocessor SoC, Telecommunications, Electrical engineering. Electronics. Nuclear engineering, Design and Optimization of Field-Programmable Gate Arrays and Application-Specific Integrated Circuits, deep sub-micrometer, Clock network

Prístupová URL adresa: https://ieeexplore.ieee.org/ielx7/6287639/9312710/09328752.pdf
https://doaj.org/article/932124f55f48463588616e9f362e2baf
https://ieeexplore.ieee.org/document/9328752
https://dblp.uni-trier.de/db/journals/access/access9.html#TehZMI21
https://doi.org/10.1109/ACCESS.2021.3053052

An Overview of Noise-Shaping SAR ADC: From Fundamentals to the Frontier

Autori: Jie Lü Xiyuan Tang Jiaxin Liu a ďalší

Zdroj: IEEE Open Journal of the Solid-State Circuits Society, Vol 1, Pp 149-161 (2021)

Predmety: Temporal Noise Analysis, Artificial intelligence, Biomedical Engineering, Synthetic aperture radar, 02 engineering and technology, Electric apparatus and materials. Electric circuits. Electric networks, Boosting (machine learning), FOS: Medical engineering, Bandwidth (computing), DSM, Engineering, CMOS Image Sensor Technology, Successive approximation ADC, FOS: Electrical engineering, electronic engineering, information engineering, 0202 electrical engineering, electronic engineering, information engineering, Computer architecture, Electrical and Electronic Engineering, TK452-454.4, Noise shaping, successive approximation, Noise-shaping, Electronic engineering, Analog Circuit Design for Biomedical Applications, Voltage, Capacitor, Low-Power VLSI Circuit Design and Optimization, Computer science, ADC, oversampling, Electrical engineering, Physical Sciences, Telecommunications, SAR

Prístupová URL adresa: https://ieeexplore.ieee.org/ielx7/8782712/9530264/09569768.pdf
https://doaj.org/article/090269d7c71743b9a299a8172c680005
https://ieeexplore.ieee.org/document/9569768