Suchergebnisse - "Java processors"

JAIP-MP: A Four-Core Java Application Processor for Embedded Systems

Autoren: Tsai, Chun-Jen Wu, Tsung-Han Su, Hung-Cheng et al.

Weitere Verfasser: Tsai, Chun-Jen Wu, Tsung-Han Su, Hung-Cheng et al.

Quelle: IFIP Advances in Information and Communication Technology ; 23th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC) ; https://inria.hal.science/hal-01578615 ; 23th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC), Oct 2015, Daejeon, South Korea. pp.170-192, ⟨10.1007/978-3-319-46097-0_9⟩

Schlagwörter: Java processors, Multi-core processors, Embedded SoC, Hardwired operating system kernel, [INFO]Computer Science [cs]

Geographisches Schlagwort: Daejeon, South Korea

Verfügbarkeit: https://inria.hal.science/hal-01578615
https://inria.hal.science/hal-01578615v1/document
https://inria.hal.science/hal-01578615v1/file/431455_1_En_9_Chapter.pdf
https://doi.org/10.1007/978-3-319-46097-0_9

Cross-Profiling for Java Processors

Autoren: Walter Binder Martin Schoeberl Philippe Moret et al.

Weitere Verfasser: Walter Binder Martin Schoeberl Philippe Moret et al.

Quelle: http://www.jopdesign.com/doc/cprof_spe.pdf.

Schlagwörter: KEY WORDS, Cross-profiling, Embedded Java processors, Bytecode instrumentation

Dateibeschreibung: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.148.544; http://www.jopdesign.com/doc/cprof_spe.pdf

Verfügbarkeit: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.148.544
http://www.jopdesign.com/doc/cprof_spe.pdf

A JAVA ILP Machine Based on Fast Dynamic Compilation

Autoren: Kemal Ebcioglu Erik Altman Erdem Hokenek et al.

Weitere Verfasser: Kemal Ebcioglu Erik Altman Erdem Hokenek et al.

Quelle: http://www.research.ibm.com/vliw/isca31/A%20JAVA%20ILP%20Machine%20Based%20on%20Fast%20Dynamic%20Compilation.pdf.

Schlagwörter: JAVA Processors, Instruction-level parallelism, Object code compatible VLIW, Dynamic compilation, Binary translation, Superscalar

Dateibeschreibung: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.60.8815; http://www.research.ibm.com/vliw/isca31/A%20JAVA%20ILP%20Machine%20Based%20on%20Fast%20Dynamic%20Compilation.pdf

Verfügbarkeit: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.60.8815
http://www.research.ibm.com/vliw/isca31/A%20JAVA%20ILP%20Machine%20Based%20on%20Fast%20Dynamic%20Compilation.pdf

Reduzindo o consumo de energia em MPSoCs heterogêneos via clock gating

Reducing energy consumption in heterogeneous MPSoCs through clock gating

Autoren: Motta, Rodrigo Bittencourt

Thesis Advisors: Wagner, Flavio Rech

Quelle: Biblioteca Digital de Teses e Dissertações da UFRGSUniversidade Federal do Rio Grande do SulUFRGS.

Schlagwörter: Microeletrônica, Sistemas embarcados, SoC, Clock gating, Heterogeneous MPSoCs, Java processors, Embedded systems

Dateibeschreibung: application/pdf

Verfügbarkeit: http://hdl.handle.net/10183/15312

Reduzindo o consumo de energia em MPSoCs heterogêneos via clock gating ; Reducing energy consumption in heterogeneous MPSoCs through clock gating

Autoren: Motta, Rodrigo Bittencourt Wagner, Flavio Rech

Weitere Verfasser: Motta, Rodrigo Bittencourt Wagner, Flavio Rech

Schlagwörter: Microeletrônica, Sistemas embarcados, SoC, Clock gating, Heterogeneous MPSoCs, Java processors, Embedded systems

Dateibeschreibung: application/pdf

Relation: http://hdl.handle.net/10183/15312; 000677257

Verfügbarkeit: http://hdl.handle.net/10183/15312

A hardware peripheral for Java bytecodes translation acceleration

Autoren: Sideris, I Moshopoulos, N Pekmestzi, K

Schlagwörter: ASIC, Java processor, RISC, stack folding, ASIC technologies, Hard task, Hardware acceleration units, Java bytecodes, Java processors, Java program, Just-in-time compilation, Speed-ups, Electric power supplies to apparatus, Embedded systems, Java programming language, Just in time production, Nanotechnology, Reduced instruction set computing, Computer software

Relation: https://dspace.lib.ntua.gr/xmlui/handle/123456789/32746; 552; 553

Verfügbarkeit: https://dspace.lib.ntua.gr/xmlui/handle/123456789/32746
https://doi.org/10.1145/1774088.1774201

A predecoding technique for ILP exploitation in Java processors

Autoren: Sideris, I Pekmestzi, K Economakos, G

Schlagwörter: ILP, Java processor, Predecoded cache, Stack folding, Computer Science, Hardware & Architecture, Computer programming languages, Decoding, Mathematical transformations, Program processors, Reduced instruction set computing, Throughput, Elsevier (CO), Execution performance, hardware accelerations, In order, Instruction-level parallelism (ILP), JAVA applications, Java bytecodes, Java processors, JAVA programs, Java Virtual Machine (JVM), Out of order, Out-of-order execution, Stack folding algorithms, super scalar, Java programming language

Relation: https://dspace.lib.ntua.gr/xmlui/handle/123456789/18572; ISI:000259160500007; 54; 707; 728

Verfügbarkeit: https://dspace.lib.ntua.gr/xmlui/handle/123456789/18572
https://doi.org/10.1016/j.sysarc.2008.01.008

Building embedded dsp applications in a Java modeling framework

Autoren: Sideris, I Pilitsos, D Economakos, G et al.

Schlagwörter: Java Language, Object Model, Statistical Model, Audio encoding, Computer architects, Cycle accurate, Embedded DSP, Error prones, Hardware designers, Java processors, Modeling frameworks, Productivity gain, Stack folding, Statistical models, SystemC, Digital signal processors, Embedded systems, Hardware, Signal processing, Java programming language

Relation: http://www.scopus.com/inward/record.url?eid=2-s2.0-84863734952&partnerID=40&md5=4ada0450939cdcf2d38776a957d391bb; http://www.microlab.ntua.gr/~isidoros/files/B2L-G03.pdf; https://dspace.lib.ntua.gr/xmlui/handle/123456789/31849; 1009; 1013

Verfügbarkeit: https://dspace.lib.ntua.gr/xmlui/handle/123456789/31849

A cache based stack folding technique for high performance Java processors

Autoren: Sideris, I Economakos, G Pekmestzi, K

Schlagwörter: ilp, Java processor, Predecoded cache, RISC, Stack folding, Algorithms, Buffer storage, Computer applications, Computer hardware, Java programming language, Reduced instruction set computing, Java processors, Stack folding algorithms, Program processors

Relation: https://dspace.lib.ntua.gr/xmlui/handle/123456789/31508; 177; 48; 57

Verfügbarkeit: https://dspace.lib.ntua.gr/xmlui/handle/123456789/31508
https://doi.org/10.1145/1167999.1168009