Suchergebnisse - "Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.)"

Improved Compact Visibility Representation of Planar Graph via Schnyder’s Realizer: Improved compact visibility representation of planar graphs via Schnyder's realizer

Autoren: Lin, C.-C. Lu, Hsueh-I Sun, I-F.

Weitere Verfasser: Lin, C.-C. Lu, Hsueh-I Sun, I-F.

Quelle: Lecture Notes in Computer Science ISBN: 9783540006237

Schlagwörter: Computational Geometry (cs.CG), FOS: Computer and information sciences, B.7.2, I.3.6, Graph representations (geometric and intersection representations, etc.), G.2.2, 0102 computer and information sciences, 01 natural sciences, graph drawing, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), Graph algorithms (graph-theoretic aspects), Graph theory (including graph drawing) in computer science, Computer graphics, computational geometry (digital and algorithmic aspects), Applications of graph theory to circuits and networks, Computer Science - Data Structures and Algorithms, Computer Science - Computational Geometry, Data Structures and Algorithms (cs.DS), canonical ordering, F.2.2, E.1, planar graph algorithm

Dateibeschreibung: application/xml

Zugangs-URL: http://arxiv.org/abs/cs/0212054
http://ntur.lib.ntu.edu.tw/bitstream/246246/214029/1/93.pdf
https://zbmath.org/2139160
https://doi.org/10.1137/s0895480103420744
https://arxiv.org/pdf/cs/0212054.pdf
https://arxiv.org/abs/cs/0212054
https://ui.adsabs.harvard.edu/abs/2002cs.......12054L/abstract

VLSI Implementation of the Multistage Detector for Next Generation Wideband CDMA Receivers: VLSI implementation of the multistage detector for next generation wideband CDMA receivers

Autoren: Xu, Gang Rajagopal, Sridhar Cavallaro, Joseph R. et al.

Weitere Verfasser: Xu, Gang Rajagopal, Sridhar Cavallaro, Joseph R. et al.

Quelle: Information Technology: Transmission, Processing and Storage ISBN: 0792376919

Schlagwörter: Computing methodologies and applications, Network design and communication in computer systems, real-time implementation, 05 social sciences, 02 engineering and technology, CDMA, multistage detection algorithm, 0508 media and communications, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), widemand code division multiple access, multiuser detection, inteference cancellation, multistage detector, 0202 electrical engineering, electronic engineering, information engineering

Dateibeschreibung: application/xml; application/pdf

Zugangs-URL: https://scholarship.rice.edu/bitstream/1911/20227/1/Raj2001May1VLSIimplem.PDF
https://zbmath.org/1747880
https://doi.org/10.1023/a:1014086523082

Embedding Problems for Paths with Direction Constrained Edges: Embedding problems for paths with direction constrained edges.

Autoren: LIOTTA, Giuseppe Whitesides S. Lubiw A. et al.

Quelle: Lecture Notes in Computer Science ISBN: 9783540677871

Schlagwörter: Shape, Embedding, Path, Rectilinear layout, General Computer Science, 0211 other engineering and technologies, 0102 computer and information sciences, 02 engineering and technology, 01 natural sciences, Theoretical Computer Science, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), Graph theory (including graph drawing) in computer science, Computer Science(all)

Dateibeschreibung: application/xml

Zugangs-URL: https://research.unipg.it/handle/11391/11368
https://link.springer.com/10.1007/3-540-44968-X_7
https://rd.springer.com/chapter/10.1007/3-540-44968-X_7
https://dblp.uni-trier.de/db/conf/cocoon/cocoon2000.html#BattistaLLW00
https://link.springer.com/chapter/10.1007%2F3-540-44968-X_7
https://iris.uniroma3.it/handle/11590/181634
https://www.sciencedirect.com/science/article/pii/S030439750100408X
https://dblp.uni-trier.de/db/journals/tcs/tcs289.html#BattistaLLW02
https://www.openaccessrepository.it/record/147072
https://hdl.handle.net/11590/181634
https://hdl.handle.net/11590/135342
http://www.sciencedirect.com/science/article/pii/S030439750100408X
https://doi.org/10.1016/S0304-3975(01)00408-X
https://hdl.handle.net/11391/11368

A complete test strategy based on interacting and hierarchical FSMs: A complete testing strategy based on interacting and hierarchical FSMs

Autoren: F. Fummi SCIUTO, DONATELLA

Quelle: Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97. 4:2709-2712

Schlagwörter: functional testing, 0209 industrial biotechnology, FSM, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, test generation, hardware description language

Dateibeschreibung: application/xml

Zugangs-URL: https://zbmath.org/1190105
https://doi.org/10.1016/s0167-9260(97)00015-1
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=612884&sortType%3Dasc_p_Sequence%26filter%3DAND%28p_IS_Number%3A13390%29
http://ieeexplore.ieee.org/iel3/4816/13390/00612884.pdf
https://iris.univr.it/handle/11562/301059
https://www.sciencedirect.com/science/article/pii/S0167926097000151
https://dblp.uni-trier.de/db/journals/integration/integration23.html#FummiS97
https://hdl.handle.net/11562/301059
https://hdl.handle.net/11562/15480
https://doi.org/10.1109/ISCAS.1997.612884
https://hdl.handle.net/11311/666804
https://hdl.handle.net/11311/665584
https://doi.org/10.1016/S0167-9260(97)00015-1

Some polynomially solvable subcases of the detailed routing problem in VLSI design

Autoren: András Recski

Quelle: Operations Research Proceedings ISBN: 9783540626305

Schlagwörter: switchbox routing, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), Applied Mathematics, VLSI design, 0202 electrical engineering, electronic engineering, information engineering, Discrete Mathematics and Combinatorics, Detailed routing, 0102 computer and information sciences, 02 engineering and technology, Channel routing, 01 natural sciences

Dateibeschreibung: application/xml

Zugangs-URL: https://zbmath.org/1699137
https://doi.org/10.1016/s0166-218x(01)00225-6
https://rd.springer.com/chapter/10.1007/978-3-642-60744-8_20
https://link.springer.com/content/pdf/10.1007%2F978-3-642-60744-8_20.pdf
https://link.springer.com/chapter/10.1007/978-3-642-60744-8_20
https://www.sciencedirect.com/science/article/pii/S0166218X01002256
https://dblp.uni-trier.de/db/journals/dam/dam115.html#Recski01
http://www.sciencedirect.com/science/article/pii/S0166218X01002256

An approximation algorithm for the register allocation problem

Autoren: Joachim Reiter Klaus Jansen

Quelle: Lecture Notes in Computer Science ISBN: 9783540631385

Schlagwörter: branching flow graphs, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), 4. Education, 0202 electrical engineering, electronic engineering, information engineering, compiling, 0102 computer and information sciences, 02 engineering and technology, register allocation, 16. Peace & justice, approximation, 7. Clean energy, 01 natural sciences

Dateibeschreibung: application/xml

Zugangs-URL: https://www.sciencedirect.com/science/article/pii/S016792609800008X
https://dblp.uni-trier.de/db/journals/integration/integration25.html#JansenR98
https://link.springer.com/10.1007/3-540-63138-0_13
https://rd.springer.com/chapter/10.1007/3-540-63138-0_13
https://dblp.uni-trier.de/db/conf/irregular/irregular97.html#JansenR97
https://link.springer.com/chapter/10.1007%2F3-540-63138-0_13

Wiring edge-disjoint layouts

Autoren: Kuchem, Ruth Wagner, Dorothea

Quelle: Lecture Notes in Computer Science ISBN: 9783540624950

Schlagwörter: Computational Mathematics, Control and Optimization, Computational Theory and Mathematics, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), Knock-knee mode, Computer graphics, computational geometry (digital and algorithmic aspects), Planar layout, VLSI-design, Geometry and Topology, layer assignment problem, Layer assignment, Computer Science Applications

Dateibeschreibung: application/xml; application/pdf

Zugangs-URL: https://link.springer.com/content/pdf/10.1007%2F3-540-62495-3_54.pdf
https://zbmath.org/1416608
https://doi.org/10.1016/s0925-7721(99)00034-6
https://www.sciencedirect.com/science/article/pii/S0925772199000346
https://dblp.uni-trier.de/db/journals/comgeo/comgeo14.html#KuchemW99
https://www.sciencedirect.com/science/article/abs/pii/S0925772199000346
https://rd.springer.com/chapter/10.1007/3-540-62495-3_54
https://kops.uni-konstanz.de/bitstream/123456789/6131/1/preprint_010.pdf
https://link.springer.com/content/pdf/10.1007%2F3-540-62495-3_54.pdf
https://link.springer.com/chapter/10.1007%2F3-540-62495-3_54
https://doi.org/10.1007/3-540-62495-3_54
https://dblp.uni-trier.de/db/conf/gd/gd1996.html#KuchemW96
http://nbn-resolving.de/urn:nbn:de:bsz:352-opus-20026

Control structures in hypothesis spaces: the influence on learning: Control structures in hypothesis spaces: The influence on learning

Autoren: Case, J. Jain, S. Suraj, M. et al.

Weitere Verfasser: Case, J. Jain, S. Suraj, M. et al.

Quelle: Lecture Notes in Computer Science ISBN: 9783540626855

Schlagwörter: Control structures, languages, computational learning theory, numberings, control structures, Computational learning theory, Inductive inference, 0102 computer and information sciences, 01 natural sciences, Theoretical Computer Science, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), Numberings, Languages, inductive inference, 0101 mathematics, Computer Science(all)

Dateibeschreibung: application/xml

Zugangs-URL: http://www.comp.nus.edu.sg/~sanjay/paps/eps.pdf
https://rd.springer.com/chapter/10.1007/3-540-62685-9_24
https://www.sciencedirect.com/science/article/pii/S0304397500003856
https://link.springer.com/chapter/10.1007/3-540-62685-9_24
https://doi.org/10.1016/S0304-3975(00)00385-6
http://www.comp.nus.edu.sg/~sanjay/paps/eps.pdf
https://www.sciencedirect.com/science/article/abs/pii/S0304397500003856
https://link.springer.com/10.1007/3-540-62685-9_24
https://dblp.uni-trier.de/db/conf/eurocolt/eurocolt1997.html#CaseJS97
https://link.springer.com/chapter/10.1007/3-540-62685-9_24

A timing-driven floorplanning algorithm with the Elmore delay model for building block layout

Autoren: Tetsushi Koide S. Wakabayashi

Quelle: VLSI: Integrated Systems on Silicon ISBN: 9781475769494

Schlagwörter: Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), building block layout, nonlinear programming, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, floorplanning, topological constraint, Elmore delay

Dateibeschreibung: application/xml

Zugangs-URL: https://link.springer.com/content/pdf/10.1007%2F978-0-387-35311-1_33.pdf
https://rd.springer.com/chapter/10.1007/978-0-387-35311-1_33
https://doi.org/10.1016/S0167-9260(98)00016-9
https://dblp.uni-trier.de/db/journals/integration/integration27.html#KoideW99
https://www.sciencedirect.com/science/article/pii/S0167926098000169
https://link.springer.com/chapter/10.1007%2F978-0-387-35311-1_33
https://link.springer.com/content/pdf/10.1007%2F978-0-387-35311-1_33.pdf

Routing on Triangles, Tori and Honeycombs: Routing on triangles, tori and honeycombs

Autoren: Sibeyn, J.

Quelle: Lecture Notes in Computer Science ISBN: 9783540615507
Mathematical Foundations of Computer Science 1996
Lecture Notes in Computer Science

Schlagwörter: Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), VLSI structures, 0202 electrical engineering, electronic engineering, information engineering, Distributed algorithms, 0102 computer and information sciences, 02 engineering and technology, 01 natural sciences, 7. Clean energy

Dateibeschreibung: application/xml

Zugangs-URL: https://core.ac.uk/display/45879320
https://link.springer.com/chapter/10.1007/3-540-61550-4_176
https://rd.springer.com/chapter/10.1007/3-540-61550-4_176
https://dblp.uni-trier.de/db/conf/mfcs/mfcs96.html#Sibeyn96
https://dblp.uni-trier.de/db/journals/ijfcs/ijfcs8.html#Sibeyn97
https://www.worldscientific.com/doi/abs/10.1142/S0129054197000185
http://pubman.mpdl.mpg.de/pubman/item/escidoc:1331578
https://pure.mpg.de/pubman/faces/ViewItemOverviewPage.jsp?itemId=item_1331578
http://hdl.handle.net/11858/00-001M-0000-0014-ABA5-8

Efficient list ranking on the reconfigurable mesh, with applications

Autoren: Koji Nakano Stephan Olariu Tatsuya Hayashi

Quelle: Lecture Notes in Computer Science ISBN: 9783540620488

Schlagwörter: list-ranking problem, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), Randomized algorithms, 0202 electrical engineering, electronic engineering, information engineering, 0102 computer and information sciences, 02 engineering and technology, Parallel algorithms in computer science, 01 natural sciences, 7. Clean energy

Dateibeschreibung: application/xml

Zugangs-URL: https://dblp.uni-trier.de/db/journals/mst/mst31.html#HayashiNO98
https://link.springer.com/article/10.1007%2Fs002240000105
https://dblp.uni-trier.de/db/conf/isaac/isaac96.html#HayashiNO96
https://link.springer.com/article/10.1007/s002240000105
https://rd.springer.com/chapter/10.1007/BFb0009509

Kolmogorov numberings and minimal identification

Autoren: Freivalds, R. Jain, S. INFORMATION SYSTEMS & COMPUTER SCIENCE

Weitere Verfasser: Freivalds, R. Jain, S. INFORMATION SYSTEMS & COMPUTER SCIENCE

Quelle: Lecture Notes in Computer Science ISBN: 9783540591191

Schlagwörter: Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), 0202 electrical engineering, electronic engineering, information engineering, Kolmogorov numberings, 0102 computer and information sciences, 02 engineering and technology, 01 natural sciences, Theoretical Computer Science, Computer Science(all)

Dateibeschreibung: application/xml

Zugangs-URL: http://www.comp.nus.edu.sg/~sanjay/paps/kol.pdf
https://dblp.uni-trier.de/db/journals/tcs/tcs188.html#FreivaldsJ97
https://www.sciencedirect.com/science/article/pii/S0304397596002952#!
https://www.sciencedirect.com/science/article/pii/S0304397596002952
https://link.springer.com/chapter/10.1007/3-540-59119-2_177
https://core.ac.uk/display/20688192
https://link.springer.com/10.1007%2F3-540-59119-2_177
https://rd.springer.com/chapter/10.1007/3-540-59119-2_177
https://dblp.uni-trier.de/db/conf/eurocolt/eurocolt1995.html#FreivaldsJ95

Bounds on the OBDD-size of integer multiplication via universal hashing

Autoren: Philipp Woelfel

Quelle: Journal of Computer and System Sciences. 71:520-534

Schlagwörter: Branching programs, Data structures, Integer multiplication, Computer Networks and Communications, Applied Mathematics, 0211 other engineering and technologies, Binary decision diagrams, 0102 computer and information sciences, 02 engineering and technology, 01 natural sciences, Theoretical Computer Science, OBDDs, Computational Theory and Mathematics, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), Computational difficulty of problems (lower bounds, completeness, difficulty of approximation, etc.)

Dateibeschreibung: application/xml

Orderly Spanning Trees with Applications: Orderly spanning trees with applications

Autoren: CHIANG, YI-TING LIN, CHING-CHI LU, HSUEH-I

Weitere Verfasser: CHIANG, YI-TING LIN, CHING-CHI LU, HSUEH-I

Quelle: SIAM Journal on Computing. 34:924-945

Schlagwörter: FOS: Computer and information sciences, Data structures, Discrete Mathematics (cs.DM), Graph representations (geometric and intersection representations, etc.), E.4, graph encoding, triangulation, G.2.2, 0102 computer and information sciences, 01 natural sciences, Graph algorithms (graph-theoretic aspects), Computer graphics, computational geometry (digital and algorithmic aspects), Applications of graph theory to circuits and networks, succinct data structure, Computer Science - Data Structures and Algorithms, F.2.2, E.1, Data Structures and Algorithms (cs.DS), canonical ordering, data compression, planar graph algorithm, unit-cost RAM model, graph drawing, realizer, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), Graph theory (including graph drawing) in computer science, visibility representation, Computer Science - Discrete Mathematics

Dateibeschreibung: application/xml; application/pdf; 293444 bytes

Zugangs-URL: http://arxiv.org/pdf/cs/0102006
http://arxiv.org/abs/cs/0102006
http://arxiv.org/pdf/cs/0102006.pdf
https://ui.adsabs.harvard.edu/abs/2001cs........2006C/abstract
https://arxiv.org/abs/cs/0102006

Designing arithmetic circuits by refinement in Ruby

Autoren: Mary Sheeran Geraint Jones

Quelle: Lecture Notes in Computer Science ISBN: 9783540566250

Schlagwörter: Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), Switching theory, application of Boolean algebra, Boolean functions, 0202 electrical engineering, electronic engineering, information engineering, Distributed algorithms, 0102 computer and information sciences, 02 engineering and technology, design by calculation, 01 natural sciences, fine-grained parallel algorithms, Software

Dateibeschreibung: application/xml

Zugangs-URL: https://www.sciencedirect.com/science/article/pii/0167642394900094
https://link.springer.com/chapter/10.1007/3-540-56625-2_15
https://dblp.uni-trier.de/db/conf/mpc/mpc92.html#JonesS92
https://core.ac.uk/display/82277377
https://rd.springer.com/chapter/10.1007%2F3-540-56625-2_15
https://link.springer.com/content/pdf/10.1007%2F3-540-56625-2_15.pdf

A linear-time algorithm for edge-disjoint paths in planar graphs

Autoren: Dorothea Wagner Karsten Weihe

Quelle: Lecture Notes in Computer Science ISBN: 9783540572732

Schlagwörter: theorem of Okamura and Seymour, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), linear-time algorithm, Graph algorithms (graph-theoretic aspects), 0211 other engineering and technologies, edge-disjoint paths, 0102 computer and information sciences, 02 engineering and technology, Paths and cycles, evenness condition, 01 natural sciences, planar graphs

Dateibeschreibung: application/xml

Zugangs-URL: https://link.springer.com/article/10.1007%2FBF01294465
https://link.springer.com/content/pdf/10.1007/BF01294465.pdf
https://dblp.uni-trier.de/db/journals/combinatorica/combinatorica15.html#WagnerW95
https://rd.springer.com/chapter/10.1007/3-540-57273-2_73
https://dblp.uni-trier.de/db/conf/esa/esa93.html#WagnerW93
https://link.springer.com/10.1007/3-540-57273-2_73
https://link.springer.com/chapter/10.1007/3-540-57273-2_73
http://www-math.mit.edu/~goemans/18438F09/wagnerweihe.pdf

THE HAUSDORFF VORONOI DIAGRAM OF POLYGONAL OBJECTS: A DIVIDE AND CONQUER APPROACH: The Hausdorff Voronoi diagram of polygonal objects: a divide and conquer approach

Autoren: Papadopoulou, E. Lee, D. T.

Weitere Verfasser: Papadopoulou, E. Lee, D. T.

Quelle: International Journal of Computational Geometry & Applications. 14:421-452

Schlagwörter: Hausdorff distance, 4. Education, via-block defects, 0102 computer and information sciences, 02 engineering and technology, Computational aspects related to convexity, 01 natural sciences, 7. Clean energy, Hausdorff-hull, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), Computer graphics, computational geometry (digital and algorithmic aspects), 0202 electrical engineering, electronic engineering, information engineering, divide and conquer, vlsi critical area, Voronoi diagram, vlsi yield

Dateibeschreibung: application/xml

Zugangs-URL: http://ntur.lib.ntu.edu.tw/bitstream/246246/200330/1/912.pdf
https://zbmath.org/2237288
https://doi.org/10.1142/s0218195904001536
https://dblp.uni-trier.de/db/journals/ijcga/ijcga14.html#PapadopoulouL04
https://www.inf.usi.ch/faculty/papadopoulou/publications/ijcga04.pdf
https://www.worldscientific.com/doi/abs/10.1142/S0218195904001536
http://ir.sinica.edu.tw/handle/201000000A/27517
https://doi.org/10.1142/S0218195904001536

Processor-efficient sparse matrix-vector multiplication

Autoren: Lenwood S. Heath Calvin J. Ribbens Sriram V. Pemmaraju

Quelle: Computers & Mathematics with Applications. 48:589-608

Schlagwörter: Staircase width, Systolic arrays, sparse matrices, Matrix-vector multiplication, Other matrix algorithms, matrix-vector multiplication, 0102 computer and information sciences, algorithms, 01 natural sciences, Computational methods for sparse matrices, Computational Mathematics, Bandwidth, staircase width, Numerical algorithms for specific classes of architectures, Computational Theory and Mathematics, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), Modelling and Simulation, Sparse matrices, systolic arrays, Stripe width, Partial orders, 0101 mathematics

Dateibeschreibung: application/xml

Zugangs-URL: https://www.sciencedirect.com/science/article/abs/pii/S0898122104840793
https://core.ac.uk/display/82699982
https://www.sciencedirect.com/science/article/pii/S0898122104840793

Mapping matrix multiplication algorithm onto fault-tolerant systolic array

Autoren: T. I. Toki T. . Milovanovi I. Stojmenovi et al.

Quelle: Computers & Mathematics with Applications. 48:275-289

Schlagwörter: Matrix multiplication, Systolic arrays, Numerical examples, Other matrix algorithms, 02 engineering and technology, 01 natural sciences, VLSI/WSI algorithms, Fault-tolerance, Computational Mathematics, Computational Theory and Mathematics, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), Modelling and Simulation, 0202 electrical engineering, electronic engineering, information engineering, 0101 mathematics

Dateibeschreibung: application/xml

Zugangs-URL: https://www.sciencedirect.com/science/article/pii/S0898122104840148
https://www.sciencedirect.com/science/article/abs/pii/S0898122104840148
https://core.ac.uk/display/82627245

SIMULATION OF MESHES WITH SEPARABLE BUSES BY MESHES WITH MULTIPLE PARTITIONED BUSES: Simulation of meshes with separable buses by meshes with multiple partitioned buses

Autoren: Susumu Matsumae

Quelle: International Journal of Foundations of Computer Science. 15:475-484

Schlagwörter: partitioned bus, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), mesh connected computer, 0202 electrical engineering, electronic engineering, information engineering, simulation algorithm, 02 engineering and technology, separable bus, Mathematical problems of computer architecture, reconfigurable mesh

Dateibeschreibung: application/xml

Zugangs-URL: https://zbmath.org/2177796
https://doi.org/10.1142/s0129054104002558
https://dblp.uni-trier.de/db/journals/ijfcs/ijfcs15.html#Matsumae04
https://doi.org/10.1142/S0129054104002558
http://doi.org/10.1142/S0129054104002558
https://www.worldscientific.com/doi/abs/10.1142/S0129054104002558
https://dblp.uni-trier.de/db/conf/ipps/ipdps2003.html#Matsumae03