Suchergebnisse - "Field-programmable gate array"

Accelerating many-core, heterogeneous, and distributed architectures with hardware runtimes and programming models

Autoren: De Haro Ruiz, Juan Miguel

Weitere Verfasser: University/Department: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors

Thesis Advisors: Álvarez Martínez, Carlos, Jiménez González, Daniel

Quelle: TDX (Tesis Doctorals en Xarxa)

Schlagwörter: High Performance Computing (HPC), Field-Programmable Gate Array (PFGA), task scheduling, task-based programming models, computer architecture, CPU, MPI, High-Level Synthesis (HLS), energy efficiency, programmability, many-core architectures, FPGA clusters, hardware runtimes, hardware acceleration, ASIC, Implicit Message Passing (IMP), Àrees temàtiques de la UPC::Informàtica, 004 - Informàtica

Dateibeschreibung: application/pdf

Zugangs-URL: http://hdl.handle.net/10803/695347
https://dx.doi.org/10.5821/dissertation-2117-442722

Application Level Synthesis: Creating Matrix-Matrix Multiplication Library: A Case Study

Autoren: Pudi, Dhilleswararao Yu, Yang Stathis, Dimitrios et al.

Quelle: IEEE Access. 12:155885-155903

Schlagwörter: Coarse grain reconfigurable architecture, field programmable gate array (FPGA), dynamically reconfigurable resource array (DRRA), distributed memory architecture (DiMArch), matrix multiplication, high-level synthesis, hardware accelerators, hardware-software co-design

Dateibeschreibung: print

Zugangs-URL: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-356494
https://doi.org/10.1109/ACCESS.2024.3484175

Hardware-Assisted Range Image Generation for LiDAR Point Clouds

Autoren: Fábio Oliveira Vitor Ferreira Sandro Pinto et al.

Weitere Verfasser: Fábio Oliveira Vitor Ferreira Sandro Pinto et al.

Quelle: IEEE Sensors Letters. 9:1-4

Schlagwörter: Light Detection and Ranging (LiDAR) sensors, Range image, Field-programmable gate array (FPGA)

Dateibeschreibung: application/pdf

Zugangs-URL: https://hdl.handle.net/1822/96443

Performance Estimation of Low Power and Area-Efficient Parallel Pipelined FFT

Autoren: P Surya C Arunachalaperumal S Dhilipkumar

Quelle: Measurement Science Review, Vol 25, Iss 3, Pp 134-140 (2025)

Schlagwörter: bit inversion technique, look-up table, field programmable gate array, low power fast fourier transform, 5g application, QA1-939, Mathematics, vedic multiplier

Zugangs-URL: https://doaj.org/article/e2cce4e2f9544eae910a1118c33071f5

Optimized Modular Adder Architecture for Cryptographic Applications on FPGAs

Autoren: Madani Bachir Azzaz Mohamed Salah Sadoudi Said et al.

Weitere Verfasser: Madani Bachir Azzaz Mohamed Salah Sadoudi Said et al.

Quelle: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 44:2168-2180

Schlagwörter: Finite field arithmetic, cryptography, Modular adder, Field Programmable Gate Array (FPGA), Ripple carry adder

Zugangs-URL: https://biblio.vub.ac.be/vubir/optimized-modular-adder-architecture-for-cryptographic-applications-on-fpgas(31db5759-8621-4387-a429-e935cbab2bdb).html

Enhanced security framework for medical data embedding based on octonionic steganographic transforms and FPGA-accelerated integrity verification

Autoren: Mohamed Amine Tahiri Ilham Karmouni Ismail Mchichou et al.

Quelle: Alexandria Engineering Journal, Vol 125, Iss, Pp 480-495 (2025)

Schlagwörter: Signal processing, Steganography, TA1-2040, Engineering (General). Civil engineering (General), Image registration, Field-programmable gate array

Zugangs-URL: https://doaj.org/article/e80259e66ac1498e919a2ba3f5f01b92

A Design Flow to Securely Isolate FPGA Bus Transactions in Heterogeneous SoCs

Autoren: Niko Salamini Sara Alonso Salazar Gabriele Serra et al.

Quelle: 2025 IEEE 31st Real-Time and Embedded Technology and Applications Symposium (RTAS). :283-295

Schlagwörter: Xilinx UltraScale+, Field-programmable gate array (FPGA), Deep Learning Processor Unit (DPU)

Dateibeschreibung: application/pdf

Zugangs-URL: https://hdl.handle.net/11382/581154
https://doi.org/10.1109/RTAS65571.2025.00035

High‐speed and reduced energy delay product TCAM on FPGA for network routers

Autoren: Sridhar Raj Sankara Vadivel Shantha Selvakumari Ramapackiam

Quelle: ETRI Journal, Vol 47, Iss 3, Pp 505-517 (2025)

Schlagwörter: field-programmable gate array, TK7800-8360, static random-access memory, Telecommunication, routers, ternary content-addressable memory, TK5101-6720, Electronics, data compression, translation lookaside buffers

Zugangs-URL: https://doaj.org/article/534a119a4ce84c34bd2ef067a85df6d9

Design and Experimental Validation Of FPGA Based Digital Control Scheme Of The Nearest Level Modulation Method For Modular Multilevel Converter Topology

Autoren: Mehmet Kurtoğlu Fatih Eroğlu Ahmet Mete Vural

Quelle: Firat University Journal of Experimental and Computational Engineering, Vol 4, Iss 1, Pp 44-58 (2025)
Volume: 4, Issue: 144-58
Firat University Journal of Experimental and Computational Engineering

Schlagwörter: field programmable gate array, modülasyon, çok seviyeli dönüştürücü, dijital kontrol, Çok seviyeli dönüştürücü, Modülasyon, Alanda programlanabilir kapı dizisi, Dijital kontrol, multilevel converter, digital control, TK1-9971, modulation, Multilevel converter, Modulation, Field programmable gate array, Digital control, Electrical Engineering (Other), Elektrik Devreleri ve Sistemleri, Electrical Circuits and Systems, Electrical engineering. Electronics. Nuclear engineering, Elektrik Mühendisliği (Diğer), alanda programlanabilir kapı dizisi

Dateibeschreibung: application/pdf

Zugangs-URL: https://doaj.org/article/805d5dcc48fd48b797d1f2373bf2d78b
https://dergipark.org.tr/tr/pub/fujece/issue/90445/1457671

AEQUAM: Accelerating Quantum Algorithm Validation Through FPGA-Based Emulation

Autoren: Lorenzo Lagostina Deborah Volpe Maurizio Zamboni et al.

Quelle: IEEE Access, Vol 13, Pp 130232-130255 (2025)

Schlagwörter: Quantum computing emulation, field programmable gate array, Quantum Physics, FOS: Electrical engineering, electronic engineering, information engineering, FOS: Physical sciences, quantum computing simulation, Electrical engineering. Electronics. Nuclear engineering, Systems and Control (eess.SY), Quantum Physics (quant-ph), Field Programmable Gate Array, Quantum Algorithm Verification, Quantum Computing Emulation, Quantum Computing Simulation, quantum algorithm verification, TK1-9971, Systems and Control

Dateibeschreibung: application/pdf

Zugangs-URL: http://arxiv.org/abs/2506.01029
https://doaj.org/article/51f724a868734b2a82c17cc87d682993
https://hdl.handle.net/11583/3002248
https://doi.org/10.1109/ACCESS.2025.3589746
https://ieeexplore.ieee.org/document/11082122

Remote Laboratory for FPGA-Based Education: A Brief Review

Autoren: Musić, Josip Kristić, Ante Prvan, Marina et al.

Quelle: Digital Transformation in Education and Artificial Intelligence Application: Third International Conference, MoStart 2025 : Proceedings. :106-123

Schlagwörter: Field Programmable Gate Array (FPGA), Remote laboratory, Distance learning

Zugangs-URL: https://link.springer.com/chapter/10.1007/978-3-032-02801-3_7

Implementation of a FPGA-Based Time-to-Digital Converter Utilizing Opposite-Transition Propagation and Virtual Bin Method

Autoren: Lee, Daehee Kwon, Sun Il

Quelle: IEEE Transactions on Radiation and Plasma Medical Sciences. 9(2)

Schlagwörter: Engineering, Electrical Engineering, Clocks, Codes, Thermometers, Temperature measurement, Radiation detectors, Delays, Coincidence timing resolution, field-programmable gate array, microchannel plate photomultiplier tube, positron emission tomography, time-of-flight, Time-of-flight, coincidence timing resolution, Clinical sciences, Oncology and carcinogenesis, Biomedical engineering

Dateibeschreibung: application/pdf

Zugangs-URL: https://escholarship.org/uc/item/7486642m
https://escholarship.org/content/qt7486642m/qt7486642m.pdf

Topology analysis and evolution trend prediction of secure propagation networks for short videos based on digital twin model

Autoren: Yu Wang Wei Liu

Quelle: Discover Computing, Vol 28, Iss 1, Pp 1-29 (2025)

Schlagwörter: Digital twins, Short video, Secure propagation, Network topology analysis, Evolution trend prediction, Field-programmable gate array, Electronic computers. Computer science, QA75.5-76.95

Dateibeschreibung: electronic resource

Relation: https://doaj.org/toc/2948-2992

Zugangs-URL: https://doaj.org/article/076e6186e5de4dabb31e9de0a2d5441b

Efficient FPGA implementation of polar codes-based information reconciliation for quantum key distribution

Autoren: Lianye Liao Xinyi Wu Ye Chen et al.

Quelle: Scientific Reports, Vol 15, Iss 1, Pp 1-12 (2025)

Schlagwörter: Field programmable gate array (FPGA), Information reconciliation (IR), Polar codes, Discrete variable quantum key distribution (DV-QKD), Medicine, Science

Dateibeschreibung: electronic resource

Relation: https://doaj.org/toc/2045-2322

Zugangs-URL: https://doaj.org/article/8ba9f13367e541dca06f202a89335c95

Development and Test of a 48-Optical Ports High-Precision Clock Distributor Board

Autoren: D. Calvet E. Molina Gonzalez HEP, INSPIRE

Weitere Verfasser: D. Calvet E. Molina Gonzalez HEP, INSPIRE

Quelle: IEEE Transactions on Nuclear Science. 72:280-286

Schlagwörter: Loop Back, Physical Experiments, jitter, Phase Variation, Optical Media, Clock Cycles, Serialized, Jitter, Synchronization, Research And Development, Peak-to-peak, Data Reception, Serial Communication, Field-programmable gate array (FPGA), Clocks, Distribution Network, precise clock distribution, Digital Filter, Eye Diagrams, High-precision Clock, User Data, Round-trip Delay, Receiver Side, Correct Alignment, Registers, Field programmable gate arrays, Detectors, Series Data, Variable Delay, Optical Fiber, End Point, Edge Detection, Ethernet, Offset Parameter, Reference Clock, [PHYS.PHYS.PHYS-INS-DET] Physics [physics]/Physics [physics]/Instrumentation and Detectors [physics.ins-det], Root Node, Optical variables measurement, Photomultiplier Tube, Phase Measurements

Exploring Dynamics and Hardware Implementation of an Enhanced 5D Hyperchaotic Memristive System Inspired by Sprott-C System

Autoren: Abdulmajeed Abdullah Mohammed Mokbel Fei Yu Yumba Musoya Gracia et al.

Quelle: Complex System Modeling and Simulation, Vol 5, Iss 1, Pp 34-45 (2025)

Schlagwörter: TA168, numerical simulation, Electronic computers. Computer science, sprott-c system, field-programmable gate array (fpga) implementation, QA75.5-76.95, memristor, hyperchaotic system, Systems engineering

Zugangs-URL: https://doaj.org/article/5dedac800e764d8bb0362f90800c70ad

C4TERO: Configurable Cascaded Carry Chains for High Reliability TERO PUFs on FPGAs

Autoren: Spagnolo, F Vatalaro, M Perri, S et al.

Quelle: IEEE Transactions on Circuits and Systems I: Regular Papers. 72:561-572

Schlagwörter: Circuit stability, field programmable gate array (FPGA), Circuits, configurable ring oscillators, Physical unclonable function, Field programmable gate arrays, carry chain, Computer architecture, Delays, high-reliability, Microprocessors, Physical unclonable function (PUF)

SYNtzulu: A Tiny RISC-V-Controlled SNN Processor for Real-Time Sensor Data Analysis on Low-Power FPGAs

Autoren: Gianluca Leone Matteo Antonio Scrugli Lorenzo Badas et al.

Quelle: ZENODO

Schlagwörter: Field programmable gate arrays, Encoding, Neurons, Computer architecture, Real-time systems, Hardware, Synapses, Spiking neural network (SNN), Edge AI, Field programmable gate array (FPGA), Energy efficiency, RISC-V

Dateibeschreibung: application/pdf

Zugangs-URL: https://ieeexplore.ieee.org/document/10666827
https://doi.org/10.1109/TCSI.2024.3450966
https://hdl.handle.net/11584/421423
https://zenodo.org/records/14170211

Design of a Drivable Area Segmentation Network Using a Field Programmable Gate Array Based on Light Detection and Ranging

Autoren: Xue-Qian Lin Jyun-Yu Jhang Cheng-Jian Lin et al.

Quelle: IEEE Access, Vol 13, Pp 130535-130548 (2025)

Schlagwörter: field programmable gate array, depthwise separable convolution, deep learning network, coordinate system, Electrical engineering. Electronics. Nuclear engineering, Drivable area segmentation, TK1-9971

Zugangs-URL: https://doaj.org/article/f1ea893e200b45adbf1b867aec264959

A Lightweight Hybrid Random Number Generator With Dynamic Entropy Injection

Autoren: Sonia Akter Shelby Williams Prosen Kirtonia et al.

Quelle: IEEE Open Journal of Circuits and Systems, Vol 6, Pp 257-269 (2025)

Schlagwörter: feedforward shift registers (FFSRs), field-programmable gate array, Internet of Things, Hybrid random number generator, National Institute of Standards and Technology (NIST), Electric apparatus and materials. Electric circuits. Electric networks, TK452-454.4, HRNG

Zugangs-URL: https://doaj.org/article/5e115f2195a247989896ce7ca50ba1c8