Suchergebnisse - "Field programmable gate array (FPGA) implementation"

Exploring Dynamics and Hardware Implementation of an Enhanced 5D Hyperchaotic Memristive System Inspired by Sprott-C System

Autoren: Abdulmajeed Abdullah Mohammed Mokbel Fei Yu Yumba Musoya Gracia et al.

Quelle: Complex System Modeling and Simulation, Vol 5, Iss 1, Pp 34-45 (2025)

Schlagwörter: TA168, numerical simulation, Electronic computers. Computer science, sprott-c system, field-programmable gate array (fpga) implementation, QA75.5-76.95, memristor, hyperchaotic system, Systems engineering

Zugangs-URL: https://doaj.org/article/5dedac800e764d8bb0362f90800c70ad

Machine learning algorithm partially reconfigured on FPGA for an image edge detection system

Autoren: Batista, Gracieth Cavalcanti Öberg, Johnny Saotome, Osamu et al.

Quelle: Journal of Electronic Science and Technology. 22(2)

Schlagwörter: Dynamic partial reconfiguration (DPR), Field programmable gate array (FPGA) implementation, Image edge detection, Support vector regression (SVR), Unmanned aerial vehicle (UAV) pose estimation

Dateibeschreibung: print

Zugangs-URL: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-346160
https://doi.org/10.1016/j.jnlest.2024.100248

An 802.11p Cross-Layered Pilot Scheme for Time- and Frequency-Varying Channels and Its Hardware Implementation

Autoren: Nagalapur, Keerthi Brännström, Fredrik Ström, Erik et al.

Quelle: IEEE Transactions on Vehicular Technology. 65(6):3917-3928

Schlagwörter: orthogonal frequency-division multiplexing (OFDM), field programmable gate array (FPGA) implementation, pilot scheme, Channel estimation, IEEE 802.11p, cross layer

Dateibeschreibung: electronic

Zugangs-URL: https://research.chalmers.se/publication/239399
http://publications.lib.chalmers.se/records/fulltext/239399/local_239399.pdf

Innovative Dual-Binary-Field Architecture for Point Multiplication of Elliptic Curve Cryptography

Autoren: Jiakun Li Weijiang Wang Jingqi Zhang et al.

Quelle: IEEE Access, Vol 9, Pp 12405-12419 (2021)

Schlagwörter: Elliptic curve cryptography (ECC), field-programmable gate array (FPGA) implementation, 0202 electrical engineering, electronic engineering, information engineering, Electrical engineering. Electronics. Nuclear engineering, 02 engineering and technology, dual-field point multiplication, montgomery ladder, TK1-9971

Zugangs-URL: https://ieeexplore.ieee.org/ielx7/6287639/9312710/09321352.pdf
https://doaj.org/article/14e86d7989614c7d849b8a3887bba9d4
https://ieeexplore.ieee.org/document/9321352
https://doi.org/10.1109/ACCESS.2021.3051282
https://dblp.uni-trier.de/db/journals/access/access9.html#LiWZLR21

Digital hardware realization of a novel adaptive ink drop spread operator and its application in modeling and classification and on-chip training

Autoren: Klidbary, S.H. Shouraki, S.B. Linares-Barranco, Bernabé et al.

Weitere Verfasser: Klidbary, S.H. Shouraki, S.B. Linares-Barranco, Bernabé et al.

Quelle: Digital.CSIC. Repositorio Institucional del CSIC
Consejo Superior de Investigaciones Científicas (CSIC)
instname

Schlagwörter: Fuzzy Modeling, Pattern Classification, Ink Drop Spread (IDS) Operator, Field-Programmable Gate Array (FPGA) Implementation, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, Soft Computing

Zugangs-URL: https://digital.csic.es/bitstream/10261/202324/1/Revise_B.pdf
http://hdl.handle.net/10261/202324
https://dblp.uni-trier.de/db/journals/mlc/mlc10.html#KlidbarySL19
https://digital.csic.es/handle/10261/202324
https://link.springer.com/article/10.1007/s13042-018-0890-x
https://doi.org/10.1007/s13042-018-0890-x
https://digital.csic.es/bitstream/10261/202324/1/Revise_B.pdf

Vulnerability Analysis of Trivium FPGA Implementations

Autoren: F. E. Potestad-Ordonez C. J. Jimenez-Fernandez M. Valencia-Barrero et al.

Weitere Verfasser: F. E. Potestad-Ordonez C. J. Jimenez-Fernandez M. Valencia-Barrero et al.

Quelle: Digital.CSIC. Repositorio Institucional del CSIC
Consejo Superior de Investigaciones Científicas (CSIC)
instname
idUS. Depósito de Investigación de la Universidad de Sevilla
Universidad de Sevilla (US)

Schlagwörter: Fault attack, field-programmable gate array (FPGA) implementation, Vulnerability analysis, Trivium, 02 engineering and technology, Stream ciphers, 01 natural sciences, 7. Clean energy, stream cipher, vulnerability analysis, 0104 chemical sciences, Stream Cipher, 13. Climate action, Implementation, 0202 electrical engineering, electronic engineering, information engineering, Field programmable gate array (FPGA), Fault Attack

Dateibeschreibung: application/pdf

Zugangs-URL: http://hdl.handle.net/10261/195257
https://hdl.handle.net/11441/105833
https://dblp.uni-trier.de/db/journals/tvlsi/tvlsi25.html#Potestad-Ordonez17
https://digital.csic.es/handle/10261/195257
https://ieeexplore.ieee.org/document/8052547
https://doi.org/10.1109/TVLSI.2017.2751151
https://idus.us.es/handle//11441/105833

High-Bandwidth Demodulation in MF-AFM: A Kalman Filtering Approach

Autoren: Ruppert, Michael G. Harcombe, David M. Moheimani, S. O. Reza et al.

Weitere Verfasser: Ruppert, Michael G. Harcombe, David M. Moheimani, S. O. Reza et al.

Quelle: IEEE/ASME Transactions on Mechatronics. 21:2705-2715

Schlagwörter: multifrequency atomic forcemicroscopy (MF-AFM), 2. Zero hunger, 0209 industrial biotechnology, Kalman filter, state estimation, 02 engineering and technology, field programmable gate array (FPGA) implementation

Zugangs-URL: https://ogma.newcastle.edu.au:443/vital/access/services/Download/uon:28415/ATTACHMENT02
https://ieeexplore.ieee.org/document/7480827/
http://ieeexplore.ieee.org/document/7480827/

A Kalman Filter for Amplitude Estimation in High-Speed Dynamic Mode Atomic Force Microscopy

Autoren: Ruppert, Michael G. Karvinen, Kai S. Wiggins, Samuel L. et al.

Weitere Verfasser: Ruppert, Michael G. Karvinen, Kai S. Wiggins, Samuel L. et al.

Quelle: IEEE Transactions on Control Systems Technology. 24:276-284

Schlagwörter: 0209 industrial biotechnology, high bandwidth, field-programmable gate array (FPGA) implementation, atomic force microscopy (AFM), Kalman filter, state estimation, 02 engineering and technology, amplitude estimation

Zugangs-URL: https://ogma.newcastle.edu.au:443/vital/access/services/Download/uon:28416/ATTACHMENT02

Adding Inverter Fault Detection to Model-Based Predictive Control for Flying-Capacitor Inverters

Autoren: Druant, Joachim Vyncke, Thomas De Belie, Frederik et al.

Quelle: IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

Schlagwörter: Technology and Engineering, CONVERTERS, DRIVE, field-programmable gate array (FPGA) implementation, SYSTEMS, single-switch fault, induction machine, RELIABILITY, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, model-based predictive control (MBPC), Fault detection

Dateibeschreibung: application/pdf

Zugangs-URL: https://biblio.ugent.be/publication/5951452/file/8724605.pdf
https://biblio.ugent.be/publication/5951452
https://ieeexplore.ieee.org/document/6891180/
https://dblp.uni-trier.de/db/journals/tie/tie62.html#DruantVBSM15
https://doi.org/10.1109/TIE.2014.2354591
https://biblio.ugent.be/publication/5951452
http://doi.org/10.1109/TIE.2014.2354591
https://biblio.ugent.be/publication/5951452/file/8724605
http://hdl.handle.net/1854/LU-5951452

Design of the Switching Controller for the High-Capacity Non-Blocking Internet Router

Autoren: Petrović, Miloš Smiljanić, Aleksandra Blagojević, Miloš

Quelle: IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Schlagwörter: high-capacity, non-blocking, Field-programmable gate-array (FPGA) implementation, 0202 electrical engineering, electronic engineering, information engineering, packet switching, 02 engineering and technology

Zugangs-URL: https://dblp.uni-trier.de/db/journals/tvlsi/tvlsi17.html#PetrovicSB09
https://ieeexplore.ieee.org/document/5067003/
http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=5067003
http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000005067003
https://www.infona.pl/resource/bwmeta1.element.ieee-art-000005067003
http://TechnoRep.tmf.bg.ac.rs/handle/123456789/1433

Optimizations of a Hardware Decoder for Deep-Space Optical Communications

Autoren: Cheng, Michael K. Nakashima, Michael A. Moision, Bruce E. et al.

Quelle: IEEE Transactions on Circuits and Systems I: Regular Papers. 55:644-658

Schlagwörter: quadratic polynomial interleaver, turbo decoding, 0508 media and communications, field-programmable gate array (FPGA) implementation, 05 social sciences, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, optical communications, 7. Clean energy, Cyclic redundancy check (CRC)

Dateibeschreibung: application/pdf

Zugangs-URL: https://ieeexplore.ieee.org/document/4400056/
https://dblp.uni-trier.de/db/journals/tcas/tcasI55.html#ChengNMH08
https://www.infona.pl/resource/bwmeta1.element.ieee-art-000004400056
http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000004400056
https://ntrs.nasa.gov/search.jsp?R=20080032378
https://repository.exst.jaxa.jp/dspace/handle/a-is/274084

Power-optimized log-based image processing system

Autoren: Dhandapani, Vaithiyanathan Ramachandran, Seshasayanan

Schlagwörter: Discrete wavelet transform (DWT), Lifting scheme, Log principles, Floating point unit (FPUs), Set partition in hierarchical trees (SPIHT), Image coding, Field-programmable gate array (FPGA) implementation, Real-time processing

Relation: http://jivp.eurasipjournals.com/content/2014/1/37

Verfügbarkeit: http://jivp.eurasipjournals.com/content/2014/1/37

A Triple-Memristor Hopfield Neural Network With Space Multi-Structure Attractors And Space Initial-Offset Behaviors

Autoren: Lin, Hairong Wang, Chunhua Yu, Fei et al.

Weitere Verfasser: Lin, Hairong Wang, Chunhua Yu, Fei et al.

Schlagwörter: Coexisting attractors, Hopfield neural network (HNN), field-programmable gate array (FPGA) implementation, initial-offset behavior, memristor synapse, multistructure attractor, Software, Electrical and Electronic Engineering, Computer Graphics and Computer-Aided Design

Relation: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems; http://hdl.handle.net/2299/26448; http://www.scopus.com/inward/record.url?scp=85162888937&partnerID=8YFLogxK

Verfügbarkeit: http://hdl.handle.net/2299/26448
http://www.scopus.com/inward/record.url?scp=85162888937&partnerID=8YFLogxK

A universal variable extension method for designing multi-scroll/wing chaotic systems

Autoren: Lin, Hairong Wang, Chunhua Sun, Yichuang et al.

Weitere Verfasser: Lin, Hairong Wang, Chunhua Sun, Yichuang et al.

Schlagwörter: Behavioral sciences, Bifurcation, Chaotic communication, Chaotic system, Design methodology, Mathematical models, Stability analysis, Thermal stability, field-programmable gate array (FPGA) implementation, initial boosting behavior, multiscroll/wing chaotic attractors (MS/WCAs), pseudorandom number generator (PRNG), Electrical and Electronic Engineering, Control and Systems Engineering

Relation: IEEE Transactions on Industrial Electronics; http://hdl.handle.net/2299/27000; http://www.scopus.com/inward/record.url?scp=85167808500&partnerID=8YFLogxK

Verfügbarkeit: http://hdl.handle.net/2299/27000
http://www.scopus.com/inward/record.url?scp=85167808500&partnerID=8YFLogxK

High-bandwidth demodulation in MF-AFM: a Kalman filtering approach

Autoren: Michael G. Ruppert David M. Harcombe S. O. Reza Moheimani

Schlagwörter: Communications engineering, Signal processing, Communications engineering not elsewhere classified, Nanotechnology, Nanometrology, field programmable gate array (FPGA) implementation, Kalman filter, multifrequency atomic forcemicroscopy (MF-AFM), state estimation

Relation: 1959.13/1340202

Verfügbarkeit: https://figshare.com/articles/journal_contribution/High-bandwidth_demodulation_in_MF-AFM_a_Kalman_filtering_approach/28966196

A Kalman filter for amplitude estimation in high-speed dynamic mode atomic force microscopy

Autoren: Michael G. Ruppert Kai S. Karvinen Samuel L. Wiggins et al.

Schlagwörter: Communications engineering, Signal processing, Control engineering, mechatronics and robotics, Nanotechnology, Nanometrology, amplitude estimation, atomic force microscopy (AFM), field-programmable gate array (FPGA) implementation, high bandwidth, Kalman filter, state estimation

Relation: 1959.13/1340203

Verfügbarkeit: https://figshare.com/articles/journal_contribution/A_Kalman_filter_for_amplitude_estimation_in_high-speed_dynamic_mode_atomic_force_microscopy/28966199

Measurement and Evaluation of Power Analysis Attacks on Asynchronous S-Box

Autoren: Wu, Jun Shi, Yiyu Choi, Minsu

Quelle: Electrical and Computer Engineering Faculty Research & Creative Works

Schlagwörter: Differential Power Analysis (DPA), Field-Programmable Gate Array (FPGA) Implementation, Null Convention Logic (NCL), Power Analysis, Security, Side-Channel Attack (SCA), Substitution Box (S-Box), Data Privacy, Differentiating Circuits, Energy Utilization, Field Programmable Gate Arrays (FPGA), Hardware, Correlation Power Analysis (CPA), Energy Consumption, Instrumentation and Measurement, Power/Noise Measurement, Electrical and Computer Engineering

Relation: https://scholarsmine.mst.edu/ele_comeng_facwork/3176; https://doi.org/10.1109/TIM.2012.2200399

Verfügbarkeit: https://scholarsmine.mst.edu/ele_comeng_facwork/3176
https://doi.org/10.1109/TIM.2012.2200399

Adaptive Viterbi Decoder for Space Communication Application

Autoren: R. V. Babar Dr. M. S. Gaikwad Pratik L. Parsewar et al.

Weitere Verfasser: R. V. Babar Dr. M. S. Gaikwad Pratik L. Parsewar et al.

Quelle: http://ijergs.org/files/documents/ADAPTIVE-58.pdf.

Schlagwörter: Adaptive Viterbi decoder, ACS unit, field-programmable gate array (FPGA) implementation

Dateibeschreibung: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.646.2191

Verfügbarkeit: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.646.2191
http://ijergs.org/files/documents/ADAPTIVE-58.pdf

Digital hardware realization of a novel adaptive ink drop spread operator and its application in modeling and classification and on-chip training

Autoren: Klidbary, S.H. Shouraki, S.B. Linares-Barranco, Bernabé

Index Begriffe: Soft Computing, Ink Drop Spread (IDS) Operator, Fuzzy Modeling, Pattern Classification, Field-Programmable Gate Array (FPGA) Implementation, artículo

URL: http://hdl.handle.net/10261/202324
Postprint
http://dx.doi.org/10.1007/s13042-018-0890-x
Sí

Vulnerability analysis of trivium FPGA implementations

Autoren: Potestad-Ordoñez, Francisco E. Jiménez Fernández, Carlos Jesús Valencia-Barrero, M.

Index Begriffe: Fault attack, field-programmable gate array (FPGA) implementation, Stream ciphers, Trivium, vulnerability analysis, artículo

URL: http://hdl.handle.net/10261/195257
https://doi.org/10.1109/TVLSI.2017.2751151
https://doi.org/10.1109/TVLSI.2017.2751151
Sí