Suchergebnisse - "Field programmable gate array (FPGA) implementation"

Field Programmable Gate Array (FPGA) Implementation of a Multi-Symbol Detection Algorithm with Reduced Matching Branches and Multiplexed Finite Impulse Response (FIR) Filters

Autoren: Kai Hong Ruifeng Duan Ling Zhao et al.

Quelle: Applied Sciences, Vol 15, Iss 4, p 2199 (2025)

Schlagwörter: PCM/FM signal, Technology, QH301-705.5, Physics, QC1-999, Engineering (General). Civil engineering (General), low complexity, Chemistry, FIR filter, TA1-2040, Biology (General), multi-symbol detection, QD1-999, FPGA

Zugangs-URL: https://doaj.org/article/f372fdddd11e475a81d7a0dfcfbd993f

Field Programmable Gate Array (FPGA) Implementation of Parallel Jacobi for Eigen-Decomposition in Direction of Arrival (DOA) Estimation Algorithm

Autoren: Shuang Zhou Li Zhou

Quelle: Remote Sensing, Vol 16, Iss 20, p 3892 (2024)

Schlagwörter: parallel Jacobi, eigen-decomposition, Science, CORDIC, FPGA

Zugangs-URL: https://doaj.org/article/21fb8e83e2e3426eaeb5519ed42e49b3

A Multiscroll Chaotic Attractors with Arrangement of Saddle-Shapes and Its Field Programmable Gate Array (FPGA) Implementation

Autoren: Faqiang Wang Yufang Xiao

Quelle: Complexity, Vol 2020 (2020)

Schlagwörter: Electronic computers. Computer science, 0103 physical sciences, QA75.5-76.95, 01 natural sciences

Dateibeschreibung: text/xhtml

Zugangs-URL: https://downloads.hindawi.com/journals/complexity/2020/9169242.pdf
https://doaj.org/article/85eef844cada47b9baf90f2b5e1d5b87
https://dblp.uni-trier.de/db/journals/complexity/complexity2020.html#WangX20a
https://downloads.hindawi.com/journals/complexity/2020/9169242.pdf
https://ideas.repec.org/a/hin/complx/9169242.html
http://downloads.hindawi.com/journals/complexity/2020/9169242.pdf
https://philpapers.org/rec/WANAMC
https://www.hindawi.com/journals/complexity/2020/9169242/

An Energy-Efficient Field-Programmable Gate Array (FPGA) Implementation of a Real-Time Perspective-n-Point Solver

Autoren: Haobo Lv Qiongzhi Wu

Quelle: Electronics. 13:3815

Smart audio mixers and field programmable gate array (FPGA) implementation / オーディオミキサのスマート化とfield programmable gate array (FPGA)による実装

Autoren: Kota Takahashi 高橋 弘太

Quelle: 日本音響学会誌 / THE JOURNAL OF THE ACOUSTICAL SOCIETY OF JAPAN. 2023, 79(12):621

Exploring Dynamics and Hardware Implementation of an Enhanced 5D Hyperchaotic Memristive System Inspired by Sprott-C System

Autoren: Abdulmajeed Abdullah Mohammed Mokbel Fei Yu Yumba Musoya Gracia et al.

Quelle: Complex System Modeling and Simulation, Vol 5, Iss 1, Pp 34-45 (2025)

Schlagwörter: TA168, numerical simulation, Electronic computers. Computer science, sprott-c system, field-programmable gate array (fpga) implementation, QA75.5-76.95, memristor, hyperchaotic system, Systems engineering

Zugangs-URL: https://doaj.org/article/5dedac800e764d8bb0362f90800c70ad

Machine learning algorithm partially reconfigured on FPGA for an image edge detection system

Autoren: Batista, Gracieth Cavalcanti Öberg, Johnny Saotome, Osamu et al.

Quelle: Journal of Electronic Science and Technology. 22(2)

Schlagwörter: Dynamic partial reconfiguration (DPR), Field programmable gate array (FPGA) implementation, Image edge detection, Support vector regression (SVR), Unmanned aerial vehicle (UAV) pose estimation

Dateibeschreibung: print

Zugangs-URL: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-346160
https://doi.org/10.1016/j.jnlest.2024.100248

Field Programmable Gate Array (FPGA) Implementation of Digital Systems: An Alternative to ASIC

Autoren: V.P. Srini

Quelle: The Fifth International Conference on VLSI Design. :309-314

Schlagwörter: 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology

Zugangs-URL: https://www.computer.org/csdl/proceedings-article/icvd/1992/00658068/12OmNAio73K
https://dblp.uni-trier.de/db/conf/vlsid/vlsid1992.html#Srini92
https://ieeexplore.ieee.org/document/658068/

Field programmable gate array (FPGA) implementation and optimization of augmented contrast limited adaptive histogram equalization

Field Programmable Gate Array (FPGA) Implementation and Optimization of Augmented Contrast Limited Adaptive Histogram Equalization

Scalable Platform for Adaptive optics Real-time Control (SPARC) Part 2: Field Programmable Gate Array (FPGA) implementation and performance

Autoren: Surendran, Avinash Burse, Mahesh P. Ramaprakash, A. N. et al.

Index Begriffe: Astrophysics - Instrumentation and Methods for Astrophysics, text

URL: http://arxiv.org/abs/1807.00715

Field programmable gate array (FPGA) implementation of novel complex PN-code-generator- based data scrambler and descrambler

Autoren: Shabir A. Parah

Quelle: Maejo International Journal of Science and Technology, Vol 4, Iss 01, Pp 125-135 (2010)

Schlagwörter: complex code generator, VHDL, FPGA, scrambler, descrambler, Technology, Technology (General), T1-995, Science, Science (General), Q1-390

Dateibeschreibung: electronic resource

Relation: http://www.mijst.mju.ac.th/vol4/125-135.pdf; https://doaj.org/toc/1905-7873

Zugangs-URL: https://doaj.org/article/0b100b42c2f441d397e2b8cfb3c01644

Field Programmable Gate Array (FPGA) Implementation of a Multi-Symbol Detection Algorithm with Reduced Matching Branches and Multiplexed Finite Impulse Response (FIR) Filters.

Autoren: Hong, Kai Duan, Ruifeng Zhao, Ling et al.

Quelle: Applied Sciences (2076-3417); Feb2025, Vol. 15 Issue 4, p2199, 16p

Schlagwörter: PULSE-code modulation, FIELD programmable gate arrays, DETECTION algorithms, FINITE impulse response filters, IMPULSE response

Field Programmable Gate Array (FPGA) Implementation of Parallel Jacobi for Eigen-Decomposition in Direction of Arrival (DOA) Estimation Algorithm.

Autoren: Zhou, Shuang Zhou, Li

Quelle: Remote Sensing; Oct2024, Vol. 16 Issue 20, p3892, 16p

Schlagwörter: FIELD programmable gate arrays, MULTIPLE Signal Classification, COVARIANCE matrices, PARALLEL processing, ELECTRONIC data processing, PARALLEL algorithms

An Energy-Efficient Field-Programmable Gate Array (FPGA) Implementation of a Real-Time Perspective-n-Point Solver.

Autoren: Lv, Haobo Wu, Qiongzhi

Quelle: Electronics (2079-9292); Oct2024, Vol. 13 Issue 19, p3815, 17p

Schlagwörter: MATRIX decomposition, GATE array circuits, MATHEMATICAL optimization, ALGORITHMS, MATRICES (Mathematics)

An 802.11p Cross-Layered Pilot Scheme for Time- and Frequency-Varying Channels and Its Hardware Implementation

Autoren: Nagalapur, Keerthi Brännström, Fredrik Ström, Erik et al.

Quelle: IEEE Transactions on Vehicular Technology. 65(6):3917-3928

Schlagwörter: orthogonal frequency-division multiplexing (OFDM), field programmable gate array (FPGA) implementation, pilot scheme, Channel estimation, IEEE 802.11p, cross layer

Dateibeschreibung: electronic

Zugangs-URL: https://research.chalmers.se/publication/239399
http://publications.lib.chalmers.se/records/fulltext/239399/local_239399.pdf

Modular Multi-Signal Tracking Pulse Descriptor Word (PDW) Generator with Field Programmable Gate Array (FPGA) Implementation

Autoren: Pelan, Justin Darrell

Quelle: Browse all Theses and Dissertations

Schlagwörter: Department of Electrical Engineering, Radar, Pulse Descriptor Words, PDW, Signal Tracking, Vhdl, Digital Hardware, Fpga, Field Programmable Gate Array, Electrical and Computer Engineering, Engineering

Dateibeschreibung: application/pdf

Relation: https://corescholar.libraries.wright.edu/etd_all/1561; https://corescholar.libraries.wright.edu/context/etd_all/article/2701/viewcontent/_etd.send_file

Verfügbarkeit: https://corescholar.libraries.wright.edu/etd_all/1561
https://corescholar.libraries.wright.edu/context/etd_all/article/2701/viewcontent/_etd.send_file

Innovative Dual-Binary-Field Architecture for Point Multiplication of Elliptic Curve Cryptography

Autoren: Jiakun Li Weijiang Wang Jingqi Zhang et al.

Quelle: IEEE Access, Vol 9, Pp 12405-12419 (2021)

Schlagwörter: Elliptic curve cryptography (ECC), field-programmable gate array (FPGA) implementation, 0202 electrical engineering, electronic engineering, information engineering, Electrical engineering. Electronics. Nuclear engineering, 02 engineering and technology, dual-field point multiplication, montgomery ladder, TK1-9971

Zugangs-URL: https://ieeexplore.ieee.org/ielx7/6287639/9312710/09321352.pdf
https://doaj.org/article/14e86d7989614c7d849b8a3887bba9d4
https://ieeexplore.ieee.org/document/9321352
https://doi.org/10.1109/ACCESS.2021.3051282
https://dblp.uni-trier.de/db/journals/access/access9.html#LiWZLR21

Field-programmable gate-array (FPGA) implementation of low-density parity-check (LDPC) decoder in digital video broadcasting - second generation satellite (DVB-S2)

Autoren: Loi, Kung Chi Cinnati

Thesis Advisors: Makaroff, Dwight, Salt, Eric J., Nguyen, Ha, Ko, Seok-Bum

Schlagwörter: FPGA, DVB-S2, LDPC

Dateibeschreibung: application/pdf

Verfügbarkeit: http://library.usask.ca/theses/available/etd-09222010-114940/

Digital hardware realization of a novel adaptive ink drop spread operator and its application in modeling and classification and on-chip training

Autoren: Klidbary, S.H. Shouraki, S.B. Linares-Barranco, Bernabé et al.

Weitere Verfasser: Klidbary, S.H. Shouraki, S.B. Linares-Barranco, Bernabé et al.

Quelle: Digital.CSIC. Repositorio Institucional del CSIC
Consejo Superior de Investigaciones Científicas (CSIC)
instname

Schlagwörter: Fuzzy Modeling, Pattern Classification, Ink Drop Spread (IDS) Operator, Field-Programmable Gate Array (FPGA) Implementation, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, Soft Computing

Zugangs-URL: https://digital.csic.es/bitstream/10261/202324/1/Revise_B.pdf
http://hdl.handle.net/10261/202324
https://dblp.uni-trier.de/db/journals/mlc/mlc10.html#KlidbarySL19
https://digital.csic.es/handle/10261/202324
https://link.springer.com/article/10.1007/s13042-018-0890-x
https://doi.org/10.1007/s13042-018-0890-x
https://digital.csic.es/bitstream/10261/202324/1/Revise_B.pdf