Výsledky vyhľadávania - "FPGA design"

Hardware and Secure Implementation of Enhanced ZUC Steam Cipher Based on Chaotic Dynamic S-Box

Autori: Madani, Mahdi Bourennane, El-Bay El Assad, Safwan a ďalší

Prispievatelia: Madani, Mahdi Bourennane, El-Bay El Assad, Safwan a ďalší

Zdroj: Advances in Science, Technology and Engineering Systems Journal. 10:37-47

Predmety: Cryptanalysis, Dynamic S-box, Mobile security, ZUC stream cipher, Hardware metrics, Cryptography, FPGA design, [INFO.INFO-CR] Computer Science [cs]/Cryptography and Security [cs.CR], [INFO.INFO-ES] Computer Science [cs]/Embedded Systems

Prístupová URL adresa: https://hal.science/hal-04928312v1
https://doi.org/10.25046/aj100105

Distributed ADMM Approach for the Power Distribution Network Reconfiguration

Predmety: Low-power high-performance VLSI design, Electromagnetic Compatibility and Noise Suppression, Electrical and Electronic Engineering, VLSI and FPGA Design Techniques

Prístupová URL adresa: https://publications.polymtl.ca/66986/

A New Hyperjerk System With a Half Line Equilibrium: Multistability, Period Doubling Reversals, Antimonotonocity, Electronic Circuit, FPGA Design, and an Application to Image Encryption

Autori: Aceng Sambas Mahdal Miroslav Sundarapandian Vaidyanathan a ďalší

Zdroj: IEEE Access, Vol 12, Pp 9177-9194 (2024)

Predmety: HyperJerk systems, chaos, chaotic systems, electronic circuit, 02 engineering and technology, 01 natural sciences, TK1-9971, multistability, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Chaos, Electrical engineering. Electronics. Nuclear engineering, FPGA design, encryption

Prístupová URL adresa: https://doaj.org/article/6e63a045ab7b4e159e293f4d243e1fe5
http://hdl.handle.net/10084/155166

HashGrid: An optimized architecture for accelerating graph computing on FPGAs

Autori: Amin Sahebi Marco Procaccini Roberto Giorgi a ďalší

Prispievatelia: Amin Sahebi Marco Procaccini Roberto Giorgi a ďalší

Predmety: Big graph computing, High-performance computing, FPGA design, Large-scale graph, Graph partitioning

Popis súboru: ELETTRONICO

Relation: info:eu-repo/semantics/altIdentifier/wos/WOS:001306729600001; volume:162; firstpage:1; lastpage:15; numberofpages:15; journal:FUTURE GENERATION COMPUTER SYSTEMS; https://hdl.handle.net/11365/1277975; https://www.sciencedirect.com/science/article/pii/S0167739X24004618

Dostupnosť: https://hdl.handle.net/11365/1277975
https://doi.org/10.1016/j.future.2024.107497
https://www.sciencedirect.com/science/article/pii/S0167739X24004618

An inspired chaos-based estimation-theory optimization for low-density parity-check (LDPC) code decoding

Autori: Fadl Dahan, Ph.D Michaelraj Kingston Roberts Munivenkatappa Nagabushanam, Ph.D a ďalší

Zdroj: Results in Engineering, Vol 22, Iss , Pp 101986- (2024)

Predmety: Chaos optimization algorithm, Bisection search method, Linear minimum mean square estimation (LMMSE), FPGA design, LDPC codes, Sustainable development goals (SDGs), Technology

Popis súboru: electronic resource

Relation: http://www.sciencedirect.com/science/article/pii/S2590123024002391; https://doaj.org/toc/2590-1230

Prístupová URL adresa: https://doaj.org/article/62cbbf4efa974739b59e909d62d6d6c7

A new hardware architecture of the adaptive vector median filter and validation in a hardware/software environment

Autori: Ben Atitallah, Ahmed Abid, Imen Boudabous, Anis a ďalší

Prispievatelia: Ben Atitallah, Ahmed Abid, Imen Boudabous, Anis a ďalší

Zdroj: International Journal of Circuit Theory and Applications. 49:2329-2347

Predmety: impulsive noise, [SPI] Engineering Sciences [physics], AVMF, 0202 electrical engineering, electronic engineering, information engineering, color image, 02 engineering and technology, FPGA design, HW/SW implementation

Prístupová URL adresa: https://dblp.uni-trier.de/db/journals/ijcta/ijcta49.html#AtitallahABL21
https://onlinelibrary.wiley.com/doi/10.1002/cta.3000

FPGA Implementation of Metaheuristic Optimization Algorithm

Autori: Nurul Hazlina Noordin Phuah Soon Eu Zuwairie Ibrahim

Zdroj: e-Prime: Advances in Electrical Engineering, Electronics and Energy, Vol 6, Iss , Pp 100377- (2023)

Predmety: FPGA design, Binary simulated Kalman filter, Electrical engineering. Electronics. Nuclear engineering, TK1-9971

Popis súboru: electronic resource

Relation: http://www.sciencedirect.com/science/article/pii/S2772671123002723; https://doaj.org/toc/2772-6711

Prístupová URL adresa: https://doaj.org/article/3bc44d2bff1748d5b14e8eeab1f5f76e

FPGA framework improvements for HPC applications

Autori: Filgueras Izquierdo, Antonio Vidal, Miquel Jiménez González, Daniel a ďalší

Prispievatelia: Filgueras Izquierdo, Antonio Vidal, Miquel Jiménez González, Daniel a ďalší

Predmety: Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, Memory management (Computer science), High performance computing, Energy consumption, HLS, HPC, Design and automation tools, FPGA, Ompss, Power efficiency, Matrix multiply, Cholesky decomposition, N-body, Spectra, Parallel programming models, FPGA design tools, High-level synthesis, Gestió de memòria (Informàtica), Càlcul intensiu (Informàtica), Energia -- Consum

Popis súboru: 2 p.; application/pdf

Relation: https://ieeexplore.ieee.org/document/10416136; info:eu-repo/grantAgreement/EC/H2020/956831/EU/Towards EXtreme scale Technologies and Accelerators for euROhpc hw%2FSw Supercomputing Applications for exascale/TEXTAROSSA; info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/PID2019-107255GB-C21/ES/BSC - COMPUTACION DE ALTAS PRESTACIONES VIII/; http://hdl.handle.net/2117/402622

Dostupnosť: http://hdl.handle.net/2117/402622
https://doi.org/10.1109/ICFPT59805.2023.00048

Farmer: an online-learning driven methodology for workload consolidation on large fpgas

Autori: Gabriele Montanaro Francesco Trovo Davide Zoni a ďalší

Prispievatelia: Gabriele Montanaro Francesco Trovo Davide Zoni a ďalší

Predmety: FPGA Design, Online Learning, Workload Consolidation, Heterogeneous SoCs, Area Optimization

Relation: ispartofbook:2025 IEEE International Symposium on Circuits and Systems (ISCAS); IEEE International Symposium on Circuits and Systems (ISCAS); firstpage:1; lastpage:5; numberofpages:5; https://hdl.handle.net/11311/1293486

Dostupnosť: https://hdl.handle.net/11311/1293486
https://doi.org/10.1109/ISCAS56072.2025.11043238

An Open-Source Hardware/Software Architecture for Remote Control of SoC-FPGA Based Systems

Autori: Werner Florian Bruno Valinoti Luis Guillermo. Garcia a ďalší

Prispievatelia: Werner Florian Bruno Valinoti Luis Guillermo. Garcia a ďalší

Zdroj: Lecture Notes in Electrical Engineering ISBN: 9783030954970

Predmety: Hardware-software codesign, System-on-chip, Embedded software, FPGA design, Real-time systems, Reconfigurable virtual instrumentation, Data acquisition systems, Hardware-software codesign System-on-chip Embedded software FPGA design Real-time systems Reconfigurable virtual instrumentation Data acquisition systems

Popis súboru: application/pdf

Prístupová URL adresa: http://hdl.handle.net/11368/3026688
https://hdl.handle.net/11368/3026688
https://link.springer.com/chapter/10.1007/978-3-030-95498-7_10
https://doi.org/10.1007/978-3-030-95498-7_10

Design for Portability of Reconfigurable Virtual Instrumentation

Autori: Mannatunga, KS Garcia Ordonez, Luis Guillermo Amador, MB a ďalší

Prispievatelia: Mannatunga, KS Garcia Ordonez, Luis Guillermo Amador, MB a ďalší

Zdroj: 2019 X Southern Conference on Programmable Logic (SPL). :45-52

Predmety: 03 medical and health sciences, 0302 clinical medicine, Hardware-Software Codesign, System-on-Chip, Embedded Software, FPGA Design, Real-Time Systems, Reconfigurable Virtual Instrumentation, Data Acquisition Systems, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, Real-Time System

Popis súboru: ELETTRONICO; application/pdf

Prístupová URL adresa: http://hdl.handle.net/11368/2952775
https://ieeexplore.ieee.org/document/8714446
https://ieeexplore.ieee.org/document/8714446/

Simple Implementation of a Fuzzy Logic Speed Controller for a PMDC Motor with a Low Cost Arduino Mega

Autori: K. S. Belkhir

Zdroj: Engineering, Technology & Applied Science Research. 10:5419-5422

Predmety: Closed loop, Artificial intelligence, Electronic speed control, Control (management), 02 engineering and technology, DC motor, Adaptive Control, Engineering, Artificial Intelligence, Analysis of Electric Machinery and Drive Systems, Fuzzy Rule-Based Systems, FOS: Electrical engineering, electronic engineering, information engineering, Control theory (sociology), 0202 electrical engineering, electronic engineering, information engineering, Type-2 Fuzzy Logic Systems and Applications, Electrical and Electronic Engineering, Fuzzy Logic Systems, Biology, FPGA Design, Transient (computer programming), Open-loop controller, Temperature control, Arduino Mega, Control engineering, Controller (irrigation), Computer hardware, Computer science, Flash memory, Agronomy, 6. Clean water, Fuzzy logic, Operating system, Origins and Applications of Electric Circuits, Electrical engineering, Computer Science, Physical Sciences, PID controller, fuzzy logic, PMDC motor

Prístupová URL adresa: https://etasr.com/index.php/ETASR/article/download/3340/pdf
https://www.etasr.com/index.php/ETASR/article/view/3340

Automation of Dynamic Power Management in FPGA-Based Energy-Constrained Systems

Autori: Michal Skuta Dominik Macko Katarina Jelemenska

Zdroj: IEEE Access, Vol 8, Pp 165894-165903 (2020)

Predmety: Internet of Things, 0202 electrical engineering, electronic engineering, information engineering, Design automation, power management, Electrical engineering. Electronics. Nuclear engineering, 02 engineering and technology, FPGA design, 7. Clean energy, energy efficiency, TK1-9971

Prístupová URL adresa: https://ieeexplore.ieee.org/ielx7/6287639/8948470/09189856.pdf
https://doaj.org/article/ce48a4e0aead4a81a463171974c5f666
https://ieeexplore.ieee.org/document/9189856/
https://dblp.uni-trier.de/db/journals/access/access8.html#SkutaMJ20

Low Power Area Optimum Configurable 160 to 2560 Subcarrier Orthogonal Frequency Division Multiplexing Modulator-Demodulator Architecture based on Systolic Array and Distributive Arithmetic Look-Up Table

Autori: G. Nanjareddy V. Mysuru Boregowda C. Prasanna Raj

Zdroj: Informacije MIDEM, Vol 51, Iss 2, Pp 119-134 (2021)

Predmety: dtcwt, optimum systolic array, folded pipelined structure, fpga design, underwater modem, low power architecture, Electronics, TK7800-8360

Popis súboru: electronic resource

Relation: http://www.midem-drustvo.si/Journal%20papers/MIDEM_51(2021)2p119.pdf; https://doaj.org/toc/0352-9045; https://doaj.org/toc/2232-6979

Prístupová URL adresa: https://doaj.org/article/51fc6f6c701c44e6acd3dfce32d581f0

Bifurcation Analysis, Synchronization and FPGA Implementation of a New 3-D Jerk System with a Stable Equilibrium

Autori: Sundarapandian Vaidyanathan Ahmad Taher Azar Ibrahim A. Hameed a ďalší

Zdroj: Mathematics ; Volume 11 ; Issue 12 ; Pages: 2623

Predmety: jerk systems, chaos, hidden attractors, bifurcation analysis, multistability, FPGA design, backstepping control

Popis súboru: application/pdf

Relation: E: Applied Mathematics; https://dx.doi.org/10.3390/math11122623

Dostupnosť: https://doi.org/10.3390/math11122623

FPGA Implementation of a Novel Multifunction Modulo (2 n ± 1) Multiplier Using Radix-4 Booth Encoding Scheme

Autori: Chao-Tsung Kuo Yao-Cheng Wu

Zdroj: Applied Sciences, Vol 13, Iss 10407, p 10407 (2023)

Predmety: residue number system, FPGA design, modulo (2 n ± 1) multiplier, parallel prefix adder, radix-4 Booth encoding, Technology, Engineering (General). Civil engineering (General), TA1-2040, Biology (General), QH301-705.5, Physics, QC1-999, Chemistry, QD1-999

Relation: https://www.mdpi.com/2076-3417/13/18/10407; https://doaj.org/toc/2076-3417; https://doaj.org/article/12a5179b92ef423ca60c36f8f164852a

Dostupnosť: https://doi.org/10.3390/app131810407
https://doaj.org/article/12a5179b92ef423ca60c36f8f164852a

Integrating Side Channel Security in the FPGA Hardware Design Flow

Autori: A. Barenghi M. Brevi W. Fornaciari a ďalší

Prispievatelia: A. Barenghi M. Brevi W. Fornaciari a ďalší

Predmety: Design automation and tools, FPGA design flow, Side channel analysis

Popis súboru: STAMPA

Relation: info:eu-repo/semantics/altIdentifier/isbn/978-3-030-68772-4; info:eu-repo/semantics/altIdentifier/isbn/978-3-030-68773-1; info:eu-repo/semantics/altIdentifier/wos/WOS:000763873700013; ispartofbook:Constructive Side-Channel Analysis and Secure Design; 11th International Workshop on Constructive Side-Channel Analysis and Secure Design (Cosade 2020); volume:12244; firstpage:275; lastpage:290; numberofpages:16; serie:LECTURE NOTES IN COMPUTER SCIENCE; alleditors:Bertoni G.M.,Regazzoni F.; http://hdl.handle.net/11311/1165568

Dostupnosť: http://hdl.handle.net/11311/1165568
https://doi.org/10.1007/978-3-030-68773-1_13
https://link.springer.com/chapter/10.1007/978-3-030-68773-1_13

Checkability of the circuits in FPGA designs according to power dissipation

Autori: V. V. Antoniuk J. V. Drozd A. V. Drozd a ďalší

Zdroj: Tekhnologiya i Konstruirovanie v Elektronnoi Apparature, Iss 1–2, Pp 3-9 (2019)

Predmety: fpga design, power dissipation monitoring, power dissipation, Electrical engineering. Electronics. Nuclear engineering, checkability of circuits, shifting register, logical form, TK1-9971

Prístupová URL adresa: https://doaj.org/article/860bdc98fa36424882c32c4ceecabe86

A Configurable IP Core for Calculating the Integer Square Root for Serial and Parallel Implementations in FPGA

Autori: Vladimir Matyukha Sergey Voloshchuk Sergey Mosin

Zdroj: Electronics, Vol 11, Iss 2335, p 2335 (2022)

Predmety: integer square root, non-restoring algorithm, FPGA design, pipelined data processing, Electronics, TK7800-8360

Relation: https://www.mdpi.com/2079-9292/11/15/2335; https://doaj.org/toc/2079-9292; https://doaj.org/article/7f0d322dd6fe4626bfb3242151636242

Dostupnosť: https://doi.org/10.3390/electronics11152335
https://doaj.org/article/7f0d322dd6fe4626bfb3242151636242

INTELLECTUAL PROPERTY CORES PROTECTION IN FPGA-BASED SPECIALIZED DEVICES ; ЗАЩИТА БЛОКОВ ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ В СПЕЦИАЛИЗИРОВАННЫХ КОМПЬЮТЕРНЫХ СРЕДСТВАХ НА БАЗЕ ПЛИС ; ЗАХИСТ БЛОКІВ ІНТЕЛЕКТУАЛЬНОЇ ВЛАСНОСТІ У СПЕЦІАЛІЗОВАНИХ КОМП’ЮТЕРНИХ ЗАСОБАХ НА БАЗІ ПЛІС

Autori: Клятченко, Ярослав Михайлович Михайлюк, Олена Станіславівна Дудкова, Лариса Миколаївна a ďalší

Zdroj: Information Technology and Computer Engineering; Vol. 50 No. 1 (2021): Information technology and computer engineering; 15-21 ; Інформаційні технології та комп'ютерна інженерія; Том 50 № 1 (2021): Інформаційні технології та комп’ютерна інженерія; 15-21 ; 2078-6387 ; 1999-9941 ; 10.31649/1999-9941-2021-50-1

Predmety: Intellectial property core, IP core, programmable logical devices, bitstream encryption, FPGA design protection, AES, HMAC, ECC, CRC, SEU, Блоки интеллектуальной собственности, IP-блоки, ПЛИС, Блоки інтелектуальної власності, ІР-блоки, ПЛІС

Popis súboru: application/pdf

Relation: https://itce.vntu.edu.ua/index.php/itce/article/view/781/518; https://itce.vntu.edu.ua/index.php/itce/article/view/781

Dostupnosť: https://itce.vntu.edu.ua/index.php/itce/article/view/781
https://doi.org/10.31649/1999-9941-2021-50-1-15-21